rockchip: jerry: Enable the Chrome OS EC

[oweals/u-boot.git] / arch / arm / dts / zynq-7000.dtsi

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a1de993b981208989965ea301480564ea701ed72..83be51ae9df65ee8c35d406d58d6dffaf25240b3 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -54,6 +54,7 @@
        };
 
        amba: amba {
+               u-boot,dm-pre-reloc;
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -135,6 +136,7 @@
                L2: cache-controller@f8f02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xF8F02000 0x1000>;
+                       interrupts = <0 2 4>;
                        arm,data-latency = <3 2 2>;
                        arm,tag-latency = <2 2 2>;
                        cache-unified;
@@ -190,6 +192,18 @@
                        #size-cells = <0>;
                };
 
+               qspi: spi@e000d000 {
+                       clock-names = "ref_clk", "pclk";
+                       clocks = <&clkc 10>, <&clkc 43>;
+                       compatible = "xlnx,zynq-qspi-1.0";
+                       status = "disabled";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 19 4>;
+                       reg = <0xe000d000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                gem0: ethernet@e000b000 {
                        compatible = "cdns,zynq-gem", "cdns,gem";
                        reg = <0xe000b000 0x1000>;
@@ -241,7 +255,6 @@
                        clkc: clkc@100 {
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
-                               ps-clk-frequency = <33333333>;
                                fclk-enable = <0>;
                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",