arm: socfpga: stratix10: Add timer support for Stratix10 SoC

[oweals/u-boot.git] / arch / arm / dts / zynq-7000.dtsi

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 6df0329cfc902f55eded63968d00c3299707db2c..47e8c184ad947f0cd17990e8da2b70909d5136fc 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Xilinx Zynq 7000 DTSI
  * Describes the hardware common to all Zynq 7000-based boards.
  *
  *  Copyright (C) 2011 - 2015 Xilinx
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 / {
@@ -16,7 +15,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@0 {
+               cpu0: cpu@0 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <0>;
@@ -30,7 +29,7 @@
                        >;
                };
 
-               cpu@1 {
+               cpu1: cpu@1 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <1>;
@@ -38,11 +37,20 @@
                };
        };
 
+       fpga_full: fpga-full {
+               compatible = "fpga-region";
+               fpga-mgr = <&devcfg>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+       };
+
        pmu@f8891000 {
                compatible = "arm,cortex-a9-pmu";
                interrupts = <0 5 4>, <0 6 4>;
                interrupt-parent = <&intc>;
-               reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+               reg = <0xf8891000 0x1000>,
+                     <0xf8893000 0x1000>;
        };
 
        regulator_vccpint: fixedregulator {
@@ -97,10 +105,10 @@
                gpio0: gpio@e000a000 {
                        compatible = "xlnx,zynq-gpio-1.0";
                        #gpio-cells = <2>;
-                       #interrupt-cells = <2>;
                        clocks = <&clkc 42>;
                        gpio-controller;
                        interrupt-controller;
+                       #interrupt-cells = <2>;
                        interrupt-parent = <&intc>;
                        interrupts = <0 20 4>;
                        reg = <0xe000a000 0x1000>;
@@ -177,7 +185,6 @@
                        interrupts = <0 26 4>;
                        clocks = <&clkc 25>, <&clkc 34>;
                        clock-names = "ref_clk", "pclk";
-                       spi-max-frequency = <166666700>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
@@ -190,7 +197,6 @@
                        interrupts = <0 49 4>;
                        clocks = <&clkc 26>, <&clkc 35>;
                        clock-names = "ref_clk", "pclk";
-                       spi-max-frequency = <166666700>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
@@ -250,12 +256,14 @@
                };
 
                slcr: slcr@f8000000 {
+                       u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
                        reg = <0xF8000000 0x1000>;
                        ranges;
                        clkc: clkc@100 {
+                               u-boot,dm-pre-reloc;
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
                                fclk-enable = <0>;