-/*
- * Device Tree Source for UniPhier PXs2 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+ X11
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
-/include/ "uniphier-common32.dtsi"
+#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "socionext,uniphier-pxs2";
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ #cooling-cells = <2>;
};
- cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ #cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu_opp>;
+ #cooling-cells = <2>;
};
};
+ cpu_opp: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ clock-latency-ns = <300>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
clocks {
- arm_timer_clk: arm_timer_clk {
- #clock-cells = <0>;
+ refclk: ref {
compatible = "fixed-clock";
- clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
};
- i2c_clk: i2c_clk {
+ arm_timer_clk: arm-timer {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
-};
-
-&soc {
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
- interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
- cache-unified;
- cache-size = <(1280 * 1024)>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
- port0x: gpio@55000008 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000008 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port1x: gpio@55000010 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000010 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port2x: gpio@55000018 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000018 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port3x: gpio@55000020 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000020 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port4: gpio@55000028 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000028 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port5x: gpio@55000030 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000030 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port6x: gpio@55000038 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000038 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
- port7x: gpio@55000040 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000040 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- port8x: gpio@55000048 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000048 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>; /* 250ms */
+ polling-delay = <1000>; /* 1000ms */
+ thermal-sensors = <&pvtctl>;
+
+ trips {
+ cpu_crit: cpu-crit {
+ temperature = <95000>; /* 95C */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ cpu_alert: cpu-alert {
+ temperature = <85000>; /* 85C */
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
};
- port9x: gpio@55000050 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000050 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+
+ l2: cache-controller@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+ <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(1280 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- port10x: gpio@55000058 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000058 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
- port12x: gpio@55000068 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000068 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ spi1: spi@54006100 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006100 0x100>;
+ interrupts = <0 216 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
- port13x: gpio@55000070 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000070 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&peri_clk 0>;
+ resets = <&peri_rst 0>;
+ };
- port14x: gpio@55000078 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000078 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&peri_clk 1>;
+ resets = <&peri_rst 1>;
+ };
- port15x: gpio@55000080 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000080 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&peri_clk 2>;
+ resets = <&peri_rst 2>;
+ };
- port16x: gpio@55000088 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000088 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&peri_clk 3>;
+ resets = <&peri_rst 3>;
+ };
- port17x: gpio@550000a0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ gpio: gpio@55000000 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000000 0x200>;
+ interrupt-parent = <&aidet>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 0>,
+ <&pinctrl 96 0 0>;
+ gpio-ranges-group-names = "gpio_range0",
+ "gpio_range1";
+ ngpios = <232>;
+ socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
+ <21 217 3>;
+ };
- port18x: gpio@550000a8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000a8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ audio@56000000 {
+ compatible = "socionext,uniphier-pxs2-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ain1>,
+ <&pinctrl_ain2>,
+ <&pinctrl_ainiec1>,
+ <&pinctrl_aout2>,
+ <&pinctrl_aout3>,
+ <&pinctrl_aoutiec1>,
+ <&pinctrl_aoutiec2>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+ socionext,syscon = <&soc_glue>;
+
+ i2s_port0: port@0 {
+ i2s_hdmi: endpoint {
+ };
+ };
+
+ i2s_port1: port@1 {
+ i2s_line: endpoint {
+ };
+ };
+
+ i2s_port2: port@2 {
+ i2s_aux: endpoint {
+ };
+ };
+
+ spdif_port0: port@3 {
+ spdif_hiecout1: endpoint {
+ };
+ };
+
+ spdif_port1: port@4 {
+ spdif_iecout1: endpoint {
+ };
+ };
+
+ comp_spdif_port0: port@5 {
+ comp_spdif_hiecout1: endpoint {
+ };
+ };
+
+ comp_spdif_port1: port@6 {
+ comp_spdif_iecout1: endpoint {
+ };
+ };
+ };
- port19x: gpio@550000b0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&peri_clk 4>;
+ resets = <&peri_rst 4>;
+ clock-frequency = <100000>;
+ };
- port20x: gpio@550000b8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000b8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&peri_clk 5>;
+ resets = <&peri_rst 5>;
+ clock-frequency = <100000>;
+ };
- port21x: gpio@550000c0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&peri_clk 6>;
+ resets = <&peri_rst 6>;
+ clock-frequency = <100000>;
+ };
- port22x: gpio@550000c8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000c8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&peri_clk 7>;
+ resets = <&peri_rst 7>;
+ clock-frequency = <100000>;
+ };
- port23x: gpio@550000d0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ /* chip-internal connection for DMD */
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ clocks = <&peri_clk 8>;
+ resets = <&peri_rst 8>;
+ clock-frequency = <400000>;
+ };
- port24x: gpio@550000d8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000d8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ /* chip-internal connection for STM */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&peri_clk 9>;
+ resets = <&peri_rst 9>;
+ clock-frequency = <400000>;
+ };
- port25x: gpio@550000e0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&peri_clk 10>;
+ resets = <&peri_rst 10>;
+ clock-frequency = <400000>;
+ };
- port26x: gpio@550000e8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000e8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ system_bus: system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ status = "disabled";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_system_bus>;
+ };
- port27x: gpio@550000f0 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f0 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ smpctrl@59801000 {
+ compatible = "socionext,uniphier-smpctrl";
+ reg = <0x59801000 0x400>;
+ };
- port28x: gpio@550000f8 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x550000f8 0x8>;
- gpio-controller;
- #gpio-cells = <2>;
- };
+ sdctrl@59810000 {
+ compatible = "socionext,uniphier-pxs2-sdctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x400>;
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ sd_clk: clock {
+ compatible = "socionext,uniphier-pxs2-sd-clock";
+ #clock-cells = <1>;
+ };
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 42 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ sd_rst: reset {
+ compatible = "socionext,uniphier-pxs2-sd-reset";
+ #reset-cells = <1>;
+ };
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-pxs2-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 44 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ peri_clk: clock {
+ compatible = "socionext,uniphier-pxs2-peri-clock";
+ #clock-cells = <1>;
+ };
- /* chip-internal connection for DMD */
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ peri_rst: reset {
+ compatible = "socionext,uniphier-pxs2-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
- /* chip-internal connection for STM */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ emmc: mmc@5a000000 {
+ compatible = "socionext,uniphier-sd-v3.1.1";
+ status = "disabled";
+ reg = <0x5a000000 0x800>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc>;
+ clocks = <&sd_clk 1>;
+ reset-names = "host", "hw";
+ resets = <&sd_rst 1>, <&sd_rst 6>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ non-removable;
+ };
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ sd: mmc@5a400000 {
+ compatible = "socionext,uniphier-sd-v3.1.1";
+ status = "disabled";
+ reg = <0x5a400000 0x800>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "uhs";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_uhs>;
+ clocks = <&sd_clk 0>;
+ reset-names = "host";
+ resets = <&sd_rst 0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
- emmc: sdhc@5a000000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a000000 0x800>;
- interrupts = <0 78 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_emmc>;
- clocks = <&mio_clk 1>;
- reset-names = "host", "hw-reset";
- resets = <&mio_rst 1>, <&mio_rst 6>;
- bus-width = <8>;
- non-removable;
- };
+ soc_glue: soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pxs2-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sdhc";
- status = "disabled";
- reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "1.8v";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_1v8>;
- clocks = <&mio_clk 0>;
- reset-names = "host";
- resets = <&mio_rst 0>;
- bus-width = <4>;
- };
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pxs2-pinctrl";
+ };
+ };
- aidet@5fc20000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x5fc20000 0x200>;
- };
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-pxs2-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x58>;
+ };
+ };
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- interrupts = <0 134 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
- };
+ aidet: interrupt-controller@5fc20000 {
+ compatible = "socionext,uniphier-pxs2-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- interrupts = <0 137 4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
- };
-};
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0xf04>;
+ clocks = <&arm_timer_clk>;
+ };
-&refclk {
- clock-frequency = <25000000>;
-};
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0xf04>;
+ clocks = <&arm_timer_clk>;
+ };
-&serial0 {
- clock-frequency = <88900000>;
-};
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
-&serial1 {
- clock-frequency = <88900000>;
-};
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-pxs2-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x10000>;
+
+ sys_clk: clock {
+ compatible = "socionext,uniphier-pxs2-clock";
+ #clock-cells = <1>;
+ };
+
+ sys_rst: reset {
+ compatible = "socionext,uniphier-pxs2-reset";
+ #reset-cells = <1>;
+ };
+
+ pvtctl: pvtctl {
+ compatible = "socionext,uniphier-pxs2-thermal";
+ interrupts = <0 3 4>;
+ #thermal-sensor-cells = <0>;
+ socionext,tmod-calibration = <0x0f86 0x6844>;
+ };
+ };
-&serial2 {
- clock-frequency = <88900000>;
-};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-pxs2-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clock-names = "ether";
+ clocks = <&sys_clk 6>;
+ reset-names = "ether";
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+ socionext,syscon-phy-mode = <&soc_glue 0>;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
-&serial3 {
- clock-frequency = <88900000>;
-};
+ _usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+ status = "disabled";
+ reg = <0x65a00000 0xcd00>;
+ interrupt-names = "host", "peripheral";
+ interrupts = <0 134 4>, <0 135 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+ clock-names = "ref", "bus_early", "suspend";
+ clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
+ resets = <&usb0_rst 15>;
+ phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
+ <&usb0_ssphy0>, <&usb0_ssphy1>;
+ dr_mode = "host";
+ };
-&mio_clk {
- compatible = "socionext,uniphier-pxs2-mio-clock";
-};
+ usb-glue@65b00000 {
+ compatible = "socionext,uniphier-pxs2-dwc3-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ usb0_rst: reset@0 {
+ compatible = "socionext,uniphier-pxs2-usb3-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
+
+ usb0_vbus0: regulator@100 {
+ compatible = "socionext,uniphier-pxs2-usb3-regulator";
+ reg = <0x100 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
+
+ usb0_vbus1: regulator@110 {
+ compatible = "socionext,uniphier-pxs2-usb3-regulator";
+ reg = <0x110 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
+
+ usb0_hsphy0: hs-phy@200 {
+ compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+ reg = <0x200 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 16>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 16>;
+ vbus-supply = <&usb0_vbus0>;
+ };
+
+ usb0_hsphy1: hs-phy@210 {
+ compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+ reg = <0x210 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 16>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 16>;
+ vbus-supply = <&usb0_vbus1>;
+ };
+
+ usb0_ssphy0: ss-phy@300 {
+ compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+ reg = <0x300 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 17>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 17>;
+ vbus-supply = <&usb0_vbus0>;
+ };
+
+ usb0_ssphy1: ss-phy@310 {
+ compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+ reg = <0x310 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 18>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 18>;
+ vbus-supply = <&usb0_vbus1>;
+ };
+ };
-&mio_rst {
- compatible = "socionext,uniphier-pxs2-mio-reset";
-};
+ /* FIXME: U-Boot own node */
+ usb0: usb@65b00000 {
+ compatible = "socionext,uniphier-pxs2-dwc3";
+ status = "disabled";
+ reg = <0x65b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+ dwc3@65a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65a00000 0x10000>;
+ interrupts = <0 134 4>;
+ dr_mode = "host";
+ tx-fifo-resize;
+ };
+ };
-&peri_clk {
- compatible = "socionext,uniphier-pxs2-peri-clock";
-};
+ _usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+ status = "disabled";
+ reg = <0x65c00000 0xcd00>;
+ interrupt-names = "host", "peripheral";
+ interrupts = <0 137 4>, <0 138 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+ clock-names = "ref", "bus_early", "suspend";
+ clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
+ resets = <&usb1_rst 15>;
+ phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
+ dr_mode = "host";
+ };
-&peri_rst {
- compatible = "socionext,uniphier-pxs2-peri-reset";
-};
+ usb-glue@65d00000 {
+ compatible = "socionext,uniphier-pxs2-dwc3-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65d00000 0x400>;
+
+ usb1_rst: reset@0 {
+ compatible = "socionext,uniphier-pxs2-usb3-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ clock-names = "link";
+ clocks = <&sys_clk 15>;
+ reset-names = "link";
+ resets = <&sys_rst 15>;
+ };
+
+ usb1_vbus0: regulator@100 {
+ compatible = "socionext,uniphier-pxs2-usb3-regulator";
+ reg = <0x100 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 15>;
+ reset-names = "link";
+ resets = <&sys_rst 15>;
+ };
+
+ usb1_vbus1: regulator@110 {
+ compatible = "socionext,uniphier-pxs2-usb3-regulator";
+ reg = <0x110 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 15>;
+ reset-names = "link";
+ resets = <&sys_rst 15>;
+ };
+
+ usb1_hsphy0: hs-phy@200 {
+ compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+ reg = <0x200 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 15>, <&sys_clk 20>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 15>, <&sys_rst 20>;
+ vbus-supply = <&usb1_vbus0>;
+ };
+
+ usb1_hsphy1: hs-phy@210 {
+ compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+ reg = <0x210 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 15>, <&sys_clk 20>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 15>, <&sys_rst 20>;
+ vbus-supply = <&usb1_vbus1>;
+ };
+
+ usb1_ssphy0: ss-phy@300 {
+ compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+ reg = <0x300 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 15>, <&sys_clk 21>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 15>, <&sys_rst 21>;
+ vbus-supply = <&usb1_vbus0>;
+ };
+ };
-&pinctrl {
- compatible = "socionext,uniphier-pxs2-pinctrl";
-};
+ /* FIXME: U-Boot own node */
+ usb1: usb@65d00000 {
+ compatible = "socionext,uniphier-pxs2-dwc3";
+ status = "disabled";
+ reg = <0x65d00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+ dwc3@65c00000 {
+ compatible = "snps,dwc3";
+ reg = <0x65c00000 0x10000>;
+ interrupts = <0 137 4>;
+ dr_mode = "host";
+ tx-fifo-resize;
+ };
+ };
-&sys_clk {
- compatible = "socionext,uniphier-pxs2-clock";
+ nand: nand-controller@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clock-names = "nand", "nand_x", "ecc";
+ clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
+ };
+ };
};
-&sys_rst {
- compatible = "socionext,uniphier-pxs2-reset";
-};
+#include "uniphier-pinctrl.dtsi"
projects / oweals / u-boot.git / blobdiff