Merge branch 'master' of git://git.denx.de/u-boot-x86

[oweals/u-boot.git] / arch / arm / dts / uniphier-ph1-pro4.dtsi

diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 244ccf67e6637712787f673229e5c5bfabed8f0b..192ce841e1379809c9efae5b456f066bbd1a507a 100644 (file)
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -64,6 +64,209 @@
                cache-level = <2>;
        };
 
+       port0x: gpio@55000008 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000008 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port1x: gpio@55000010 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000010 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port2x: gpio@55000018 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000018 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port3x: gpio@55000020 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000020 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port4: gpio@55000028 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000028 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port5x: gpio@55000030 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000030 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port6x: gpio@55000038 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000038 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port7x: gpio@55000040 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000040 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port8x: gpio@55000048 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000048 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port9x: gpio@55000050 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000050 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port10x: gpio@55000058 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000058 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port11x: gpio@55000060 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000060 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port12x: gpio@55000068 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000068 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port13x: gpio@55000070 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000070 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port14x: gpio@55000078 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000078 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port17x: gpio@550000a0 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000a0 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port18x: gpio@550000a8 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000a8 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port19x: gpio@550000b0 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000b0 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port20x: gpio@550000b8 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000b8 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port21x: gpio@550000c0 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000c0 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port22x: gpio@550000c8 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000c8 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port23x: gpio@550000d0 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000d0 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port24x: gpio@550000d8 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000d8 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port25x: gpio@550000e0 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000e0 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port26x: gpio@550000e8 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000e8 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port27x: gpio@550000f0 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000f0 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port28x: gpio@550000f8 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x550000f8 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port29x: gpio@55000100 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000100 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       port30x: gpio@55000108 {
+               compatible = "socionext,uniphier-gpio";
+               reg = <0x55000108 0x8>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
        i2c0: i2c@58780000 {
                compatible = "socionext,uniphier-fi2c";
                status = "disabled";
@@ -140,6 +343,43 @@
                clock-frequency = <400000>;
        };
 
+       sd: sdhc@5a400000 {
+               compatible = "socionext,uniphier-sdhc";
+               status = "disabled";
+               reg = <0x5a400000 0x200>;
+               interrupts = <0 76 4>;
+               pinctrl-names = "default", "1.8v";
+               pinctrl-0 = <&pinctrl_sd>;
+               pinctrl-1 = <&pinctrl_sd_1v8>;
+               clocks = <&mio_clk 0>;
+               bus-width = <4>;
+       };
+
+       emmc: sdhc@5a500000 {
+               compatible = "socionext,uniphier-sdhc";
+               status = "disabled";
+               reg = <0x5a500000 0x200>;
+               interrupts = <0 78 4>;
+               pinctrl-names = "default", "1.8v";
+               pinctrl-0 = <&pinctrl_emmc>;
+               pinctrl-1 = <&pinctrl_emmc_1v8>;
+               clocks = <&mio_clk 1>;
+               bus-width = <8>;
+               non-removable;
+       };
+
+       sd1: sdhc@5a600000 {
+               compatible = "socionext,uniphier-sdhc";
+               status = "disabled";
+               reg = <0x5a600000 0x200>;
+               interrupts = <0 85 4>;
+               pinctrl-names = "default", "1.8v";
+               pinctrl-0 = <&pinctrl_sd1>;
+               pinctrl-1 = <&pinctrl_sd1_1v8>;
+               clocks = <&mio_clk 2>;
+               bus-width = <4>;
+       };
+
        usb2: usb@5a800100 {
                compatible = "socionext,uniphier-ehci", "generic-ehci";
                status = "disabled";
@@ -147,6 +387,7 @@
                interrupts = <0 80 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb2>;
+               clocks = <&mio_clk 3>, <&mio_clk 6>;
        };
 
        usb3: usb@5a810100 {
@@ -156,6 +397,12 @@
                interrupts = <0 81 4>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usb3>;
+               clocks = <&mio_clk 4>, <&mio_clk 6>;
+       };
+
+       aidet@5fc20000 {
+               compatible = "simple-mfd", "syscon";
+               reg = <0x5fc20000 0x200>;
        };
 
        usb0: usb@65a00000 {
@@ -177,6 +424,10 @@
        };
 };
 
+&refclk {
+       clock-frequency = <25000000>;
+};
+
 &serial0 {
        clock-frequency = <73728000>;
 };
@@ -193,6 +444,30 @@
        clock-frequency = <73728000>;
 };
 
+&mio_clk {
+       compatible = "socionext,uniphier-pro4-mio-clock";
+};
+
+&mio_rst {
+       compatible = "socionext,uniphier-pro4-mio-reset";
+};
+
+&peri_clk {
+       compatible = "socionext,uniphier-pro4-peri-clock";
+};
+
+&peri_rst {
+       compatible = "socionext,uniphier-pro4-peri-reset";
+};
+
 &pinctrl {
-       compatible = "socionext,ph1-pro4-pinctrl", "syscon";
+       compatible = "socionext,uniphier-pro4-pinctrl";
+};
+
+&sys_clk {
+       compatible = "socionext,uniphier-pro4-clock";
+};
+
+&sys_rst {
+       compatible = "socionext,uniphier-pro4-reset";
 };