Merge tag 'u-boot-imx-20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

[oweals/u-boot.git] / arch / arm / dts / tegra30-apalis.dts

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 13ab42bf3dcab6832bc9bda215c8f32dc0f5ce41..77502dfdb4783f83f8dc535fdec1b1a87774824a 100644 (file)
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -15,9 +15,9 @@
                i2c1 = "/i2c@7000c000";
                i2c2 = "/i2c@7000c500";
                i2c3 = "/i2c@7000c700";
-               sdhci0 = "/sdhci@78000600";
-               sdhci1 = "/sdhci@78000400";
-               sdhci2 = "/sdhci@78000000";
+               mmc0 = "/sdhci@78000600";
+               mmc1 = "/sdhci@78000400";
+               mmc2 = "/sdhci@78000000";
                spi0 = "/spi@7000d400";
                spi1 = "/spi@7000dc00";
                spi2 = "/spi@7000de00";
@@ -32,7 +32,7 @@
                reg = <0x80000000 0x40000000>;
        };
 
-       pcie-controller@00003000 {
+       pcie@3000 {
                status = "okay";
                avdd-pexa-supply = <&vdd2_reg>;
                vdd-pexa-supply = <&vdd2_reg>;
@@ -43,14 +43,19 @@
                vddio-pex-ctl-supply = <&sys_3v3_reg>;
                hvdd-pex-supply = <&sys_3v3_reg>;
 
+               /* Apalis Type Specific 4 Lane PCIe */
                pci@1,0 {
+                       /* TS_DIFF1/2/3/4 left disabled */
                        nvidia,num-lanes = <4>;
                };
 
+               /* Apalis PCIe */
                pci@2,0 {
+                       /* PCIE1_RX/TX left disabled */
                        nvidia,num-lanes = <1>;
                };
 
+               /* I210 Gigabit Ethernet Controller (On-module) */
                pci@3,0 {
                        status = "okay";
                        nvidia,num-lanes = <1>;
@@ -63,7 +68,7 @@
         */
        i2c@7000c000 {
                status = "okay";
-               clock-frequency = <100000>;
+               clock-frequency = <400000>;
        };
 
        /* GEN2_I2C: unused */
@@ -74,13 +79,13 @@
         */
        i2c@7000c500 {
                status = "okay";
-               clock-frequency = <100000>;
+               clock-frequency = <400000>;
        };
 
        /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
        i2c@7000c700 {
                status = "okay";
-               clock-frequency = <100000>;
+               clock-frequency = <10000>;
        };
 
        /*
@@ -114,9 +119,6 @@
                        vccio-supply = <&sys_3v3_reg>;
 
                        regulators {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-
                                /* SW1: +V1.35_VDDIO_DDR */
                                vdd1_reg: vdd1 {
                                        regulator-name = "vddio_ddr_1v35";
@@ -267,7 +269,7 @@
        /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
        usb@7d000000 {
                status = "okay";
-               dr_mode = "peripheral";
+               dr_mode = "otg";
                /* USBO1_EN */
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
        };
@@ -277,7 +279,6 @@
                status = "okay";
                /* USBH_EN */
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
-               phy_type = "utmi";
        };
 
        /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -287,6 +288,26 @@
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clk@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+               clk16m: clk@1 {
+                       compatible = "fixed-clock";
+                       reg=<1>;
+                       #clock-cells = <0>;
+                       clock-frequency = <16000000>;
+                       clock-output-names = "clk16m";
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -311,3 +332,7 @@
                };
        };
 };
+
+&uarta {
+       status = "okay";
+};