Merge git://git.denx.de/u-boot-dm

[oweals/u-boot.git] / arch / arm / dts / tegra30-apalis.dts

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 60e87a4f3af51209e973aa0ed7b9077935220dc3..0b84dae2157f655d990f5aa7154872f4e3479dec 100644 (file)
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -44,10 +44,12 @@
                hvdd-pex-supply = <&sys_3v3_reg>;
 
                pci@1,0 {
+                       /* TS_DIFF1/2/3/4 left disabled */
                        nvidia,num-lanes = <4>;
                };
 
                pci@2,0 {
+                       /* PCIE1_RX/TX left disabled */
                        nvidia,num-lanes = <1>;
                };
 
@@ -63,7 +65,7 @@
         */
        i2c@7000c000 {
                status = "okay";
-               clock-frequency = <100000>;
+               clock-frequency = <400000>;
        };
 
        /* GEN2_I2C: unused */
@@ -74,13 +76,13 @@
         */
        i2c@7000c500 {
                status = "okay";
-               clock-frequency = <100000>;
+               clock-frequency = <400000>;
        };
 
        /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
        i2c@7000c700 {
                status = "okay";
-               clock-frequency = <100000>;
+               clock-frequency = <10000>;
        };
 
        /*
@@ -277,7 +279,6 @@
                status = "okay";
                /* USBH_EN */
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
-               phy_type = "utmi";
        };
 
        /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -287,6 +288,26 @@
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clk@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+               clk16m: clk@1 {
+                       compatible = "fixed-clock";
+                       reg=<1>;
+                       #clock-cells = <0>;
+                       clock-frequency = <16000000>;
+                       clock-output-names = "clk16m";
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -311,3 +332,7 @@
                };
        };
 };
+
+&uarta {
+       status = "okay";
+};