Merge tag 'u-boot-imx-20191009' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
[oweals/u-boot.git] / arch / arm / dts / tegra20-trimslice.dts
index 27b118f212ad7bec41953dd6e2c18c8da8c431b9..e19001ee2bdfdfc6e074c9beaa3158ee0ec3cb0f 100644 (file)
        };
 
        aliases {
-               usb0 = "/usb@c5008000";
-               usb1 = "/usb@c5000000";
-               sdhci0 = "/sdhci@c8000600";
-               sdhci1 = "/sdhci@c8000000";
+               usb0 = "/usb@c5000000";
+               mmc0 = "/sdhci@c8000600";
+               mmc1 = "/sdhci@c8000000";
                spi0 = "/spi@7000c380";
        };
 
                clock-frequency = <216000000>;
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
        spi@7000c380 {
                status = "okay";
                spi-max-frequency = <25000000>;
        };
 
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
-       i2c@7000d000 {
-               status = "disabled";
-       };
-
-       pcie-controller@80003000 {
+       pcie@80003000 {
                status = "okay";
 
                avdd-pex-supply = <&pci_vdd_reg>;
        };
 
        usb@c5000000 {
+               status = "okay";
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
        };
 
-       usb@c5004000 {
-               status = "disabled";
-       };
-
        sdhci@c8000000 {
                status = "okay";
                bus-width = <4>;
                bus-width = <4>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
        };
 
 };
+
+&uarta {
+       status = "okay";
+};