ARM: tegra: add PCIe controller to Tegra186 SoC DT
[oweals/u-boot.git] / arch / arm / dts / tegra20-paz00.dts
index 9d735b5e6bf6541b3dbfb0974cc3ee668d129d02..5c7e80558da355426033ebbf4bfd6bd60b0d6a71 100644 (file)
@@ -20,7 +20,7 @@
                reg = <0x00000000 0x20000000>;
        };
 
-       host1x {
+       host1x@50000000 {
                status = "okay";
                dc@54200000 {
                        status = "okay";
                clock-frequency = < 216000000 >;
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
-       i2c@7000d000 {
-               status = "disabled";
-       };
-
-       usb@c5000000 {
-               status = "disabled";
-       };
-
-       usb@c5004000 {
-               status = "disabled";
+       usb@c5008000 {
+               status = "okay";
        };
 
        sdhci@c8000000 {
                status = "okay";
-               cd-gpios = <&gpio 173 1>; /* gpio PV5 */
-               wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-               power-gpios = <&gpio 169 0>; /* gpio PV1 */
+               cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
+               wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+               power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
        };
 
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
+       pwm: pwm@7000a000 {
+               status = "okay";
+       };
+
        lcd_panel: panel {
                /* PAZ00 has 1024x600 */
                clock = <54030000>;
                hsync-active-high;
                nvidia,bits-per-pixel = <16>;
                nvidia,pwm = <&pwm 0 0>;
-               nvidia,backlight-enable-gpios = <&gpio 164 0>;  /* PU4 */
-               nvidia,lvds-shutdown-gpios = <&gpio 102 0>;     /* PM6 */
-               nvidia,backlight-vdd-gpios = <&gpio 176 0>;     /* PW0 */
-               nvidia,panel-vdd-gpios = <&gpio 4 0>;           /* PA4 */
+               nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
+                                                       GPIO_ACTIVE_HIGH>;
+               nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
+                                                       GPIO_ACTIVE_HIGH>;
+               nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
+                                                       GPIO_ACTIVE_HIGH>;
+               nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
+                                                       GPIO_ACTIVE_HIGH>;
                nvidia,panel-timings = <400 4 203 17 15>;
        };
 };