ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / dts / sun8i-h3.dtsi

diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index f0096074a46786cf36c6a824aa6a7ce8bba824ac..20217e2ca4d3a5792f22f9186c63b167a03db301 100644 (file)
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -47,19 +47,19 @@
                compatible = "operating-points-v2";
                opp-shared;
 
-               opp@648000000 {
+               opp-648000000 {
                        opp-hz = /bits/ 64 <648000000>;
                        opp-microvolt = <1040000 1040000 1300000>;
                        clock-latency-ns = <244144>; /* 8 32k periods */
                };
 
-               opp@816000000 {
+               opp-816000000 {
                        opp-hz = /bits/ 64 <816000000>;
                        opp-microvolt = <1100000 1100000 1300000>;
                        clock-latency-ns = <244144>; /* 8 32k periods */
                };
 
-               opp@1008000000 {
+               opp-1008000000 {
                        opp-hz = /bits/ 64 <1008000000>;
                        opp-microvolt = <1200000 1200000 1300000>;
                        clock-latency-ns = <244144>; /* 8 32k periods */
@@ -80,7 +80,7 @@
                        #cooling-cells = <2>;
                };
 
-               cpu@1 {
+               cpu1: cpu@1 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
                        reg = <1>;
@@ -90,7 +90,7 @@
                        #cooling-cells = <2>;
                };
 
-               cpu@2 {
+               cpu2: cpu@2 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
                        reg = <2>;
@@ -100,7 +100,7 @@
                        #cooling-cells = <2>;
                };
 
-               cpu@3 {
+               cpu3: cpu@3 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
                        reg = <3>;
@@ -111,6 +111,15 @@
                };
        };
 
+       pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       };
+
        timer {
                compatible = "arm,armv7-timer";
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -120,9 +129,22 @@
        };
 
        soc {
-               system-control@1c00000 {
+               deinterlace: deinterlace@1400000 {
+                       compatible = "allwinner,sun8i-h3-deinterlace";
+                       reg = <0x01400000 0x20000>;
+                       clocks = <&ccu CLK_BUS_DEINTERLACE>,
+                                <&ccu CLK_DEINTERLACE>,
+                                <&ccu CLK_DRAM_DEINTERLACE>;
+                       clock-names = "bus", "mod", "ram";
+                       resets = <&ccu RST_BUS_DEINTERLACE>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       interconnects = <&mbus 9>;
+                       interconnect-names = "dma-mem";
+               };
+
+               syscon: system-control@1c00000 {
                        compatible = "allwinner,sun8i-h3-system-control";
-                       reg = <0x01c00000 0x30>;
+                       reg = <0x01c00000 0x1000>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
@@ -142,6 +164,26 @@
                        };
                };
 
+               video-codec@1c0e000 {
+                       compatible = "allwinner,sun8i-h3-video-engine";
+                       reg = <0x01c0e000 0x1000>;
+                       clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+                                <&ccu CLK_DRAM_VE>;
+                       clock-names = "ahb", "mod", "ram";
+                       resets = <&ccu RST_BUS_VE>;
+                       interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                       allwinner,sram = <&ve_sram 1>;
+               };
+
+               crypto: crypto@1c15000 {
+                       compatible = "allwinner,sun8i-h3-crypto";
+                       reg = <0x01c15000 0x1000>;
+                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+                       clock-names = "bus", "mod";
+                       resets = <&ccu RST_BUS_CE>;
+               };
+
                mali: gpu@1c40000 {
                        compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
                        reg = <0x01c40000 0x10000>;
@@ -166,6 +208,26 @@
                        assigned-clocks = <&ccu CLK_GPU>;
                        assigned-clock-rates = <384000000>;
                };
+
+               ths: thermal-sensor@1c25000 {
+                       compatible = "allwinner,sun8i-h3-ths";
+                       reg = <0x01c25000 0x400>;
+                       interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&ccu RST_BUS_THS>;
+                       clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+                       clock-names = "bus", "mod";
+                       nvmem-cells = <&ths_calibration>;
+                       nvmem-cell-names = "calibration";
+                       #thermal-sensor-cells = <0>;
+               };
+       };
+
+       thermal-zones {
+               cpu_thermal: cpu-thermal {
+                       polling-delay-passive = <0>;
+                       polling-delay = <0>;
+                       thermal-sensors = <&ths 0>;
+               };
        };
 };
 
@@ -216,3 +278,11 @@
 &pio {
        compatible = "allwinner,sun8i-h3-pinctrl";
 };
+
+&rtc {
+       compatible = "allwinner,sun8i-h3-rtc";
+};
+
+&sid {
+       compatible = "allwinner,sun8i-h3-sid";
+};