Merge branch 'master' of git://git.denx.de/u-boot

[oweals/u-boot.git] / arch / arm / dts / sun5i-a13.dtsi

diff --git a/arch/arm/dts/sun5i-a13.dtsi b/arch/arm/dts/sun5i-a13.dtsi
index 0188deed6f75714916d3a255bef4a917c8d32df7..b1d827765530f9369916825e3fd499fd3f34e1dc 100644 (file)
--- a/arch/arm/dts/sun5i-a13.dtsi
+++ b/arch/arm/dts/sun5i-a13.dtsi
@@ -18,11 +18,6 @@
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
- *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
- *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- *     MA 02110-1301 USA
- *
  * Or, alternatively,
  *
  *  b) Permission is hereby granted, free of charge, to any person
@@ -51,26 +46,11 @@
 
 #include "sun5i.dtsi"
 
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
        interrupt-parent = <&intc>;
 
-       chosen {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               ranges;
-
-               framebuffer@0 {
-                       compatible = "allwinner,simple-framebuffer",
-                                    "simple-framebuffer";
-                       allwinner,pipeline = "de_be0-lcd0";
-                       clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
-                       status = "disabled";
-               };
-       };
-
        thermal-zones {
                cpu_thermal {
                        /* milliseconds */
@@ -88,7 +68,7 @@
                        trips {
                                cpu_alert0: cpu_alert0 {
                                        /* milliCelsius */
-                                       temperature = <850000>;
+                                       temperature = <85000>;
                                        hysteresis = <2000>;
                                        type = "passive";
                                };
@@ -103,69 +83,41 @@
                };
        };
 
-       clocks {
-               ahb_gates: clk@01c20060 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun5i-a13-ahb-gates-clk";
-                       reg = <0x01c20060 0x8>;
-                       clocks = <&ahb>;
-                       clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
-                               "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
-                               "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
-                               "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
-                               "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
-                               "ahb_de_fe", "ahb_iep", "ahb_mali400";
-               };
+       display-engine {
+               compatible = "allwinner,sun5i-a13-display-engine";
+               allwinner,pipelines = <&fe0>;
+       };
 
-               apb0_gates: clk@01c20068 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun5i-a13-apb0-gates-clk";
-                       reg = <0x01c20068 0x4>;
-                       clocks = <&apb0>;
-                       clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
+       soc@1c00000 {
+               pwm: pwm@1c20e00 {
+                       compatible = "allwinner,sun5i-a13-pwm";
+                       reg = <0x01c20e00 0xc>;
+                       clocks = <&ccu CLK_HOSC>;
+                       #pwm-cells = <3>;
+                       status = "disabled";
                };
 
-               apb1_gates: clk@01c2006c {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun5i-a13-apb1-gates-clk";
-                       reg = <0x01c2006c 0x4>;
-                       clocks = <&apb1>;
-                       clock-output-names = "apb1_i2c0", "apb1_i2c1",
-                               "apb1_i2c2", "apb1_uart1", "apb1_uart3";
-               };
        };
 };
 
+&ccu {
+       compatible = "allwinner,sun5i-a13-ccu";
+};
+
 &cpu0 {
        clock-latency = <244144>; /* 8 32k periods */
        operating-points = <
-               /* kHz    uV */
+               /* kHz    uV */
                1008000 1400000
-               912000  1350000
-               864000  1300000
-               624000  1200000
-               576000  1200000
-               432000  1200000
+               912000  1350000
+               864000  1300000
+               624000  1200000
+               576000  1200000
+               432000  1200000
                >;
        #cooling-cells = <2>;
-       cooling-min-level = <0>;
-       cooling-max-level = <5>;
 };
 
 &pio {
        compatible = "allwinner,sun5i-a13-pinctrl";
-
-       uart1_pins_a: uart1@0 {
-               allwinner,pins = "PE10", "PE11";
-               allwinner,function = "uart1";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-       };
-
-       uart1_pins_b: uart1@1 {
-               allwinner,pins = "PG3", "PG4";
-               allwinner,function = "uart1";
-               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-       };
 };