Merge branch 'master' of git://git.denx.de/u-boot

[oweals/u-boot.git] / arch / arm / dts / stm32mp157c-ed1-u-boot.dtsi

diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index 5b8be93512b5fac4cb261da2877f515f9dd76ea6..ed2f024be9810d5cdc78c073a231f1ee7d16099e 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -4,48 +4,57 @@
  */
 
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
-#include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-u-boot.dtsi"
 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
 
 / {
        aliases {
+               i2c3 = &i2c4;
                mmc0 = &sdmmc1;
                mmc1 = &sdmmc2;
-               i2c3 = &i2c4;
        };
-};
 
-&uart4_pins_a {
-       u-boot,dm-pre-reloc;
-       pins1 {
-               u-boot,dm-pre-reloc;
+       config {
+               u-boot,boot-led = "heartbeat";
+               u-boot,error-led = "error";
+               st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+               st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
        };
-       pins2 {
-               u-boot,dm-pre-reloc;
+
+       led {
+               red {
+                       label = "error";
+                       gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+                       default-state = "off";
+                       status = "okay";
+               };
+
+               blue {
+                       default-state = "on";
+               };
        };
 };
 
-&i2c4_pins_a {
-       u-boot,dm-pre-reloc;
-       pins {
-               u-boot,dm-pre-reloc;
-       };
+&clk_hse {
+       st,digbypass;
 };
 
-&uart4 {
+&i2c4 {
        u-boot,dm-pre-reloc;
 };
 
-&i2c4 {
+&i2c4_pins_a {
        u-boot,dm-pre-reloc;
+       pins {
+               u-boot,dm-pre-reloc;
+       };
 };
 
 &pmic {
        u-boot,dm-pre-reloc;
 };
 
-/* CLOCK init */
-&rcc_clk {
+&rcc {
        st,clksrc = <
                CLK_MPU_PLL1P
                CLK_AXI_PLL2P
@@ -73,22 +82,47 @@
        >;
 
        st,pkcs = <
-               CLK_CKPER_DISABLED
-               CLK_SDMMC12_PLL3R
+               CLK_CKPER_HSE
+               CLK_FMC_ACLK
+               CLK_QSPI_ACLK
+               CLK_ETH_DISABLED
+               CLK_SDMMC12_PLL4P
+               CLK_DSI_DSIPLL
                CLK_STGEN_HSE
-               CLK_I2C46_PCLK5
-               CLK_I2C12_PCLK1
-               CLK_SDMMC3_PLL3R
-               CLK_I2C35_PCLK1
-               CLK_UART1_PCLK5
-               CLK_UART24_PCLK1
-               CLK_UART35_PCLK1
-               CLK_UART6_PCLK2
-               CLK_UART78_PCLK1
+               CLK_USBPHY_HSE
+               CLK_SPI2S1_PLL3Q
+               CLK_SPI2S23_PLL3Q
+               CLK_SPI45_HSI
+               CLK_SPI6_HSI
+               CLK_I2C46_HSI
+               CLK_SDMMC3_PLL4P
+               CLK_USBO_USBPHY
+               CLK_ADC_CKPER
+               CLK_CEC_LSE
+               CLK_I2C12_HSI
+               CLK_I2C35_HSI
+               CLK_UART1_HSI
+               CLK_UART24_HSI
+               CLK_UART35_HSI
+               CLK_UART6_HSI
+               CLK_UART78_HSI
+               CLK_SPDIF_PLL4P
+               CLK_FDCAN_PLL4R
+               CLK_SAI1_PLL3Q
+               CLK_SAI2_PLL3Q
+               CLK_SAI3_PLL3Q
+               CLK_SAI4_PLL3Q
+               CLK_RNG1_LSI
+               CLK_RNG2_LSI
+               CLK_LPTIM1_PCLK1
+               CLK_LPTIM23_PCLK3
+               CLK_LPTIM45_LSE
        >;
 
        /* VCO = 1300.0 MHz => P = 650 (CPU) */
        pll1: st,pll@0 {
+               compatible = "st,stm32mp1-pll";
+               reg = <0>;
                cfg = < 2 80 0 0 0 PQR(1,0,0) >;
                frac = < 0x800 >;
                u-boot,dm-pre-reloc;
@@ -96,48 +130,65 @@
 
        /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
        pll2: st,pll@1 {
+               compatible = "st,stm32mp1-pll";
+               reg = <1>;
                cfg = < 2 65 1 0 0 PQR(1,1,1) >;
                frac = < 0x1400 >;
                u-boot,dm-pre-reloc;
        };
 
-       /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
+       /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
        pll3: st,pll@2 {
-               cfg = < 3 128 3 20 7 PQR(1,1,1) >;
+               compatible = "st,stm32mp1-pll";
+               reg = <2>;
+               cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+               frac = < 0x1a04 >;
                u-boot,dm-pre-reloc;
        };
 
-       /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
+       /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
        pll4: st,pll@3 {
-               cfg = < 5 126 8 8 8 PQR(1,1,1) >;
+               compatible = "st,stm32mp1-pll";
+               reg = <3>;
+               cfg = < 3 98 5 7 7 PQR(1,1,1) >;
                u-boot,dm-pre-reloc;
        };
 };
 
-/* SPL part **************************************/
-/* MMC1 boot */
+&sdmmc1 {
+       u-boot,dm-spl;
+};
+
 &sdmmc1_b4_pins_a {
        u-boot,dm-spl;
-       pins {
+       pins1 {
+               u-boot,dm-spl;
+       };
+       pins2 {
                u-boot,dm-spl;
        };
 };
 
 &sdmmc1_dir_pins_a {
        u-boot,dm-spl;
-       pins {
+       pins1 {
+               u-boot,dm-spl;
+       };
+       pins2 {
                u-boot,dm-spl;
        };
 };
 
-&sdmmc1 {
+&sdmmc2 {
        u-boot,dm-spl;
 };
 
-/* MMC2 boot */
 &sdmmc2_b4_pins_a {
        u-boot,dm-spl;
-       pins {
+       pins1 {
+               u-boot,dm-spl;
+       };
+       pins2 {
                u-boot,dm-spl;
        };
 };
@@ -149,6 +200,18 @@
        };
 };
 
-&sdmmc2 {
-       u-boot,dm-spl;
+&uart4 {
+       u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+       u-boot,dm-pre-reloc;
+       pins1 {
+               u-boot,dm-pre-reloc;
+       };
+       pins2 {
+               u-boot,dm-pre-reloc;
+               /* pull-up on rx to avoid floating level */
+               bias-pull-up;
+       };
 };