+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2018
- *
- * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
/ {
soc {
- ddr: ddr@0x5A003000{
+ ddr: ddr@5a003000 {
u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-ddr";
reg = <0x5A003000 0x550
0x5A004000 0x234>;
- clocks = <&rcc_clk AXIDCG>,
- <&rcc_clk DDRC1>,
- <&rcc_clk DDRC2>,
- <&rcc_clk DDRPHYC>,
- <&rcc_clk DDRCAPB>,
- <&rcc_clk DDRPHYCAPB>;
+ clocks = <&rcc AXIDCG>,
+ <&rcc DDRC1>,
+ <&rcc DDRC2>,
+ <&rcc DDRPHYC>,
+ <&rcc DDRCAPB>,
+ <&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
DDR_MR3
>;
+#ifdef DDR_PHY_CAL_SKIP
st,phy-cal = <
DDR_DX0DLLCR
DDR_DX0DQTR
DDR_DX3DQSTR
>;
+#endif
+
status = "okay";
};
};