#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
clocks {
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
+ clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
u-boot,dm-pre-reloc;
};
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <92>;
spi-max-frequency = <108000000>;
- clocks = <&rcc 0 65>;
+ clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
status = "disabled";
};
usart1: serial@40011000 {
- compatible = "st,stm32-usart", "st,stm32-uart";
+ compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
- clocks = <&rcc 0 164>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
status = "disabled";
u-boot,dm-pre-reloc;
};
+
+ pwrcfg: power-config@58024800 {
+ compatible = "syscon";
+ reg = <0x40007000 0x400>;
+ };
+
rcc: rcc@40023810 {
#reset-cells = <1>;
#clock-cells = <2>;
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ compatible = "st,stm32f746-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
+ st,syscfg = <&pwrcfg>;
u-boot,dm-pre-reloc;
};
u-boot,dm-pre-reloc;
pins-are-numbered;
- usart1_pins_a: usart1@0 {
+ gpioa: gpio@40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x0 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
+ st,bank-name = "GPIOA";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x400 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
+ st,bank-name = "GPIOB";
+ u-boot,dm-pre-reloc;
+ };
+
+
+ gpioc: gpio@40020800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x800 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
+ st,bank-name = "GPIOC";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpiod: gpio@40020c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0xc00 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
+ st,bank-name = "GPIOD";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpioe: gpio@40021000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x1000 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
+ st,bank-name = "GPIOE";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpiof: gpio@40021400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x1400 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
+ st,bank-name = "GPIOF";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpiog: gpio@40021800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x1800 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
+ st,bank-name = "GPIOG";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpioh: gpio@40021c00 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x1c00 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
+ st,bank-name = "GPIOH";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpioi: gpio@40022000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x2000 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
+ st,bank-name = "GPIOI";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpioj: gpio@40022400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x2400 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
+ st,bank-name = "GPIOJ";
+ u-boot,dm-pre-reloc;
+ };
+
+ gpiok: gpio@40022800 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ compatible = "st,stm32-gpio";
+ reg = <0x2800 0x400>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
+ st,bank-name = "GPIOK";
+ u-boot,dm-pre-reloc;
+ };
+
+ sdio_pins: sdio_pins@0 {
+ pins {
+ pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+ <STM32F746_PC9_FUNC_SDMMC1_D1>,
+ <STM32F746_PC10_FUNC_SDMMC1_D2>,
+ <STM32F746_PC11_FUNC_SDMMC1_D3>,
+ <STM32F746_PC12_FUNC_SDMMC1_CK>,
+ <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od@0 {
pins1 {
- pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
- bias-disable;
+ pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+ <STM32F746_PC9_FUNC_SDMMC1_D1>,
+ <STM32F746_PC10_FUNC_SDMMC1_D2>,
+ <STM32F746_PC11_FUNC_SDMMC1_D3>,
+ <STM32F746_PC12_FUNC_SDMMC1_CK>;
drive-push-pull;
slew-rate = <2>;
};
+
pins2 {
- pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
- bias-disable;
+ pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+ drive-open-drain;
+ slew-rate = <2>;
};
};
- ethernet_mii: mii@0 {
+
+ sdio_pins_b: sdio_pins_b@0 {
pins {
- pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
- <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
- <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
- <STM32F746_PA2_FUNC_ETH_MDIO>,
- <STM32F746_PC1_FUNC_ETH_MDC>,
- <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
- <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
- <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
- <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+ pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+ <STM32F769_PG10_FUNC_SDMMC2_D1>,
+ <STM32F769_PB3_FUNC_SDMMC2_D2>,
+ <STM32F769_PB4_FUNC_SDMMC2_D3>,
+ <STM32F769_PD6_FUNC_SDMMC2_CLK>,
+ <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+ drive-push-pull;
slew-rate = <2>;
};
};
- qspi_pins: qspi@0{
- pins {
- pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
- <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
- <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
- <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
- <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
- <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+
+ sdio_pins_od_b: sdio_pins_od_b@0 {
+ pins1 {
+ pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+ <STM32F769_PG10_FUNC_SDMMC2_D1>,
+ <STM32F769_PB3_FUNC_SDMMC2_D2>,
+ <STM32F769_PB4_FUNC_SDMMC2_D3>,
+ <STM32F769_PD6_FUNC_SDMMC2_CLK>;
+ drive-push-pull;
slew-rate = <2>;
};
- };
- fmc_pins: fmc@0 {
- pins {
- pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
- <STM32F746_PD9_FUNC_FMC_D14>,
- <STM32F746_PD8_FUNC_FMC_D13>,
- <STM32F746_PE15_FUNC_FMC_D12>,
- <STM32F746_PE14_FUNC_FMC_D11>,
- <STM32F746_PE13_FUNC_FMC_D10>,
- <STM32F746_PE12_FUNC_FMC_D9>,
- <STM32F746_PE11_FUNC_FMC_D8>,
- <STM32F746_PE10_FUNC_FMC_D7>,
- <STM32F746_PE9_FUNC_FMC_D6>,
- <STM32F746_PE8_FUNC_FMC_D5>,
- <STM32F746_PE7_FUNC_FMC_D4>,
- <STM32F746_PD1_FUNC_FMC_D3>,
- <STM32F746_PD0_FUNC_FMC_D2>,
- <STM32F746_PD15_FUNC_FMC_D1>,
- <STM32F746_PD14_FUNC_FMC_D0>,
-
- <STM32F746_PE1_FUNC_FMC_NBL1>,
- <STM32F746_PE0_FUNC_FMC_NBL0>,
-
- <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
- <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
-
- <STM32F746_PG1_FUNC_FMC_A11>,
- <STM32F746_PG0_FUNC_FMC_A10>,
- <STM32F746_PF15_FUNC_FMC_A9>,
- <STM32F746_PF14_FUNC_FMC_A8>,
- <STM32F746_PF13_FUNC_FMC_A7>,
- <STM32F746_PF12_FUNC_FMC_A6>,
- <STM32F746_PF5_FUNC_FMC_A5>,
- <STM32F746_PF4_FUNC_FMC_A4>,
- <STM32F746_PF3_FUNC_FMC_A3>,
- <STM32F746_PF2_FUNC_FMC_A2>,
- <STM32F746_PF1_FUNC_FMC_A1>,
- <STM32F746_PF0_FUNC_FMC_A0>,
-
- <STM32F746_PH3_FUNC_FMC_SDNE0>,
- <STM32F746_PH5_FUNC_FMC_SDNWE>,
- <STM32F746_PF11_FUNC_FMC_SDNRAS>,
- <STM32F746_PG15_FUNC_FMC_SDNCAS>,
- <STM32F746_PC3_FUNC_FMC_SDCKE0>,
- <STM32F746_PG8_FUNC_FMC_SDCLK>;
+ pins2 {
+ pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+ drive-open-drain;
slew-rate = <2>;
};
};
};
+ sdio: sdio@40012c00 {
+ compatible = "st,stm32f4xx-sdio";
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ interrupts = <49>;
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ pinctrl-names = "default", "opendrain";
+ max-frequency = <48000000>;
+ };
+
+ sdio2: sdio2@40011c00 {
+ compatible = "st,stm32f4xx-sdio";
+ reg = <0x40011c00 0x400>;
+ clocks = <&rcc 0 167>;
+ interrupts = <103>;
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins_b>;
+ pinctrl-1 = <&sdio_pins_od_b>;
+ pinctrl-names = "default", "opendrain";
+ max-frequency = <48000000>;
+ };
};
};
projects / oweals / u-boot.git / blobdiff