// SPDX-License-Identifier: GPL-2.0+
+#include <dt-bindings/memory/stm32-sdram.h>
/{
soc {
u-boot,dm-pre-reloc;
};
qspi: quadspi@A0001000 {
- compatible = "st,stm32-qspi";
+ compatible = "st,stm32f469-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
};
&gpioa {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
- compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
-&gpioj {
- compatible = "st,stm32-gpio";
-};
-
-&gpiok {
- compatible = "st,stm32-gpio";
-};
-
&pinctrl {
u-boot,dm-pre-reloc;
u-boot,dm-pre-reloc;
};
};
-
- usart1_pins_a: usart1@0 {
- u-boot,dm-pre-reloc;
- pins1 {
- u-boot,dm-pre-reloc;
- };
- pins2 {
- u-boot,dm-pre-reloc;
- };
- };
};
&pwrcfg {
&usart1 {
u-boot,dm-pre-reloc;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
};