ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / dts / stm32f469-disco-u-boot.dtsi

diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index a980ac46f5668b2dccd696fcb86701645bbc2af6..5a89f130548c295aeaa0bb336df96460e5580c6e 100644 (file)
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -23,6 +23,7 @@
                gpio8 = &gpioi;
                gpio9 = &gpioj;
                gpio10 = &gpiok;
+               spi0 = &qspi;
        };
 
        soc {
@@ -64,6 +65,19 @@
                               st,sdram-refcount = < 1292 >;
                       };
                };
+
+               qspi: quadspi@A0001000 {
+                       compatible = "st,stm32f469-qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+                       reg-names = "qspi", "qspi_mm";
+                       interrupts = <91>;
+                       spi-max-frequency = <108000000>;
+                       clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
+                       resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
+                       pinctrl-0 = <&qspi_pins>;
+               };
        };
 };
 
@@ -80,57 +94,46 @@
 };
 
 &gpioa {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpiob {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpioc {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpiod {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpioe {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpiof {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpiog {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpioh {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpioi {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpioj {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
 &gpiok {
-       compatible = "st,stm32-gpio";
        u-boot,dm-pre-reloc;
 };
 
@@ -205,6 +208,18 @@
                };
        };
 
+       qspi_pins: qspi@0 {
+               pins {
+                       pinmux = <STM32_PINMUX('F',10, AF9)>, /* CLK */
+                                <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
+                                <STM32_PINMUX('F', 8, AF10)>, /* BK1_IO0 */
+                                <STM32_PINMUX('F', 9, AF10)>, /* BK1_IO1 */
+                                <STM32_PINMUX('F', 7, AF9)>, /* BK1_IO2 */
+                                <STM32_PINMUX('F', 6, AF9)>; /* BK1_IO3 */
+                       slew-rate = <2>;
+               };
+       };
+
        usart3_pins_a: usart3@0 {
                u-boot,dm-pre-reloc;
                pins1 {
@@ -227,3 +242,16 @@
 &syscfg {
        u-boot,dm-pre-reloc;
 };
+
+&qspi {
+       reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
+       flash0: n25q128a {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <108000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+               reg = <0>;
+       };
+};