Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clk

[oweals/u-boot.git] / arch / arm / dts / socfpga_cyclone5_sr1500.dts

diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index e24830af57edc1e5f41b3ec7c257005c0f2f5849..bb29da6d6c926c24138bf3aa5b9e69f015a4b288 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -1,10 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
 
 / {
        model = "SoCFPGA Cyclone V SR1500";
@@ -12,6 +12,7 @@
 
        chosen {
                bootargs = "console=ttyS0,115200";
+               stdout-path = "serial0:115200n8";
        };
 
        aliases {
@@ -27,10 +28,6 @@
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
        };
-
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &gmac1 {
@@ -50,6 +47,18 @@
        status = "okay";
 };
 
+&porta {
+       bank-name = "porta";
+};
+
+&portb {
+       bank-name = "portb";
+};
+
+&portc {
+       bank-name = "portc";
+};
+
 &i2c0 {
        status = "okay";
        speed-mode = <0>;
@@ -68,6 +77,7 @@
 
 &uart0 {
        status = "okay";
+       u-boot,dm-pre-reloc;
 };
 
 &usb1 {
@@ -86,7 +96,7 @@
                u-boot,dm-pre-reloc;
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00", "spi-flash";
+               compatible = "n25q00", "jedec,spi-nor";
                reg = <0>;      /* chip select */
                spi-max-frequency = <100000000>;
                m25p,fast-read;