+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
/ {
model = "SoCFPGA Cyclone V IS1";
chosen {
bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
};
memory {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&gmac1 {
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
+ txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ rxc-skew-ps = <1200>;
};
&gpio1 {
status = "okay";
};
+&porta {
+ bank-name = "porta";
+};
+
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00";
+ compatible = "n25q00", "jedec,spi-nor";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
&usb1 {
status = "okay";
};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&watchdog0 {
+ status = "disabled";
+};