ARM: dts: rmobile: Add soc label to Gen3

[oweals/u-boot.git] / arch / arm / dts / socfpga_arria10.dtsi

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 2f935a21e95ce33ce41328d6d3987af38b3cafc7..2c5249c1eb4ff93f5e7aa0899ee68a46d39bb462 100644 (file)
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -21,6 +21,11 @@
        #address-cells = <1>;
        #size-cells = <1>;
 
+       chosen {
+               tick-timer = &timer2;
+               u-boot,dm-pre-reloc;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -55,6 +60,7 @@
                device_type = "soc";
                interrupt-parent = <&intc>;
                ranges;
+               u-boot,dm-pre-reloc;
 
                amba {
                        compatible = "simple-bus";
@@ -93,29 +99,35 @@
                clkmgr@ffd04000 {
                                compatible = "altr,clk-mgr";
                                reg = <0xffd04000 0x1000>;
+                               u-boot,dm-pre-reloc;
 
                                clocks {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
+                                       u-boot,dm-pre-reloc;
 
                                        cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        cb_intosc_ls_clk: cb_intosc_ls_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        f2s_free_clk: f2s_free_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        osc1: osc1 {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        main_pll: main_pll@40 {
@@ -126,6 +138,7 @@
                                                clocks = <&osc1>, <&cb_intosc_ls_clk>,
                                                         <&f2s_free_clk>;
                                                reg = <0x40>;
+                                               u-boot,dm-pre-reloc;
 
                                                main_mpu_base_clk: main_mpu_base_clk {
                                                        #clock-cells = <0>;
@@ -139,6 +152,7 @@
                                                        compatible = "altr,socfpga-a10-perip-clk";
                                                        clocks = <&main_pll>;
                                                        div-reg = <0x144 0 11>;
+                                                       u-boot,dm-pre-reloc;
                                                };
 
                                                main_emaca_clk: main_emaca_clk@68 {
@@ -214,6 +228,7 @@
                                                clocks = <&osc1>, <&cb_intosc_ls_clk>,
                                                         <&f2s_free_clk>, <&main_periph_ref_clk>;
                                                reg = <0xC0>;
+                                               u-boot,dm-pre-reloc;
 
                                                peri_mpu_base_clk: peri_mpu_base_clk {
                                                        #clock-cells = <0>;
@@ -227,6 +242,7 @@
                                                        compatible = "altr,socfpga-a10-perip-clk";
                                                        clocks = <&periph_pll>;
                                                        div-reg = <0x144 16 11>;
+                                                       u-boot,dm-pre-reloc;
                                                };
 
                                                peri_emaca_clk: peri_emaca_clk@e8 {
@@ -302,6 +318,7 @@
                                                         <&osc1>, <&cb_intosc_hs_div2_clk>,
                                                         <&f2s_free_clk>;
                                                reg = <0x64>;
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        s2f_user1_free_clk: s2f_user1_free_clk@104 {
@@ -328,6 +345,7 @@
                                                compatible = "altr,socfpga-a10-perip-clk";
                                                clocks = <&noc_free_clk>;
                                                fixed-divider = <4>;
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        l4_main_clk: l4_main_clk {
@@ -427,8 +445,8 @@
                        rx-fifo-depth = <16384>;
                        clocks = <&l4_mp_clk>;
                        clock-names = "stmmaceth";
-                       resets = <&rst EMAC0_RESET>;
-                       reset-names = "stmmaceth";
+                       resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+                       reset-names = "stmmaceth", "stmmaceth-ocp";
                        snps,axi-config = <&socfpga_axi_setup>;
                        status = "disabled";
                };
@@ -447,8 +465,8 @@
                        rx-fifo-depth = <16384>;
                        clocks = <&l4_mp_clk>;
                        clock-names = "stmmaceth";
-                       resets = <&rst EMAC1_RESET>;
-                       reset-names = "stmmaceth";
+                       resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+                       reset-names = "stmmaceth", "stmmaceth-ocp";
                        snps,axi-config = <&socfpga_axi_setup>;
                        status = "disabled";
                };
@@ -467,6 +485,8 @@
                        rx-fifo-depth = <16384>;
                        clocks = <&l4_mp_clk>;
                        clock-names = "stmmaceth";
+                       resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+                       reset-names = "stmmaceth", "stmmaceth-ocp";
                        snps,axi-config = <&socfpga_axi_setup>;
                        status = "disabled";
                };
@@ -547,6 +567,8 @@
                        reg = <0xffc02200 0x100>;
                        interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
+                       resets = <&rst I2C0_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -557,6 +579,8 @@
                        reg = <0xffc02300 0x100>;
                        interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
+                       resets = <&rst I2C1_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -567,6 +591,8 @@
                        reg = <0xffc02400 0x100>;
                        interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
+                       resets = <&rst I2C2_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -577,6 +603,8 @@
                        reg = <0xffc02500 0x100>;
                        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
+                       resets = <&rst I2C3_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -587,6 +615,8 @@
                        reg = <0xffc02600 0x100>;
                        interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
+                       resets = <&rst I2C4_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -643,6 +673,7 @@
                        interrupts = <0 99 4>;
                        dma-mask = <0xffffffff>;
                        clocks = <&nand_clk>;
+                       resets = <&rst NAND_RESET>;
                        status = "disabled";
                };
 
@@ -717,7 +748,7 @@
                };
 
                qspi: spi@ff809000 {
-                       compatible = "cdns,qspi-nor", "cadence,qspi";
+                       compatible = "cdns,qspi-nor";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0xff809000 0x100>,
@@ -735,6 +766,7 @@
                        compatible = "altr,rst-mgr";
                        reg = <0xffd05000 0x100>;
                        altr,modrst-offset = <0x20>;
+                       u-boot,dm-pre-reloc;
                };
 
                scu: snoop-control-unit@ffffc000 {
@@ -778,6 +810,7 @@
                        reg = <0xffd00000 0x100>;
                        clocks = <&l4_sys_free_clk>;
                        clock-names = "timer";
+                       u-boot,dm-pre-reloc;
                };
 
                timer3: timer3@ffd00100 {
@@ -795,6 +828,7 @@
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        clocks = <&l4_sp_clk>;
+                       resets = <&rst UART0_RESET>;
                        status = "disabled";
                };
 
@@ -805,6 +839,7 @@
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        clocks = <&l4_sp_clk>;
+                       resets = <&rst UART1_RESET>;
                        status = "disabled";
                };