Merge tag 'u-boot-imx-20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

[oweals/u-boot.git] / arch / arm / dts / rk3368-px5-evb-u-boot.dtsi

diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
index 3a5e30ea55128068af61aca56ae90ffc3afa9822..002767a0330ea35bf4b0268a213bf056ca5ebb63 100644 (file)
--- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -1,8 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
  * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier:     GPL-2.0+       X11
  */
+/ {
+       chosen {
+               u-boot,spl-boot-order = &emmc;
+       };
+};
+
+&dmc {
+       u-boot,dm-pre-reloc;
+
+       /*
+        * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
+        * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
+        * details on the 'rockchip,memory-schedule' property and how it
+        * affects the physical-address to device-address mapping.
+        */
+       rockchip,memory-schedule = <DMC_MSCH_CBRD>;
+       rockchip,ddr-frequency = <800000000>;
+       rockchip,ddr-speed-bin = <DDR3_1600K>;
+
+       status = "okay";
+};
 
 &pinctrl {
        u-boot,dm-pre-reloc;
@@ -21,6 +41,10 @@
        u-boot,dm-pre-reloc;
 };
 
+&sgrf {
+       u-boot,dm-pre-reloc;
+};
+
 &cru {
        u-boot,dm-pre-reloc;
 };
@@ -32,3 +56,13 @@
 &uart4 {
        u-boot,dm-pre-reloc;
 };
+
+&emmc {
+       u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+       u-boot,dm-pre-reloc;
+       clock-frequency = <24000000>;
+       status = "okay";
+};