i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ mmc2 = &sdmmc_ext;
};
cpus {
};
grf: syscon@ff100000 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
#address-cells = <1>;
status = "disabled";
};
+ dmc: dmc@ff400000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3328-dmc", "syscon";
+ reg = <0x0 0xff400000 0x0 0x1000>;
+ };
+
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
sdmmc: rksdmmc@ff500000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff500000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
sdio: dwmmc@ff510000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff510000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
emmc: rksdmmc@ff520000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff520000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
status = "disabled";
};
+ gmac2io: ethernet@ff540000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff540000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
+ <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
+ <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
+ <&cru PCLK_MAC2IO>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru SRST_GMAC2IO_A>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@ff5c0000 {
compatible = "generic-ehci";
reg = <0x0 0xff5c0000 0x0 0x10000>;
status = "disabled";
};
+ usb20_otg: usb@ff580000 {
+ compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff580000 0x0 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ hnp-srp-disable;
+ dr_mode = "otg";
+ status = "disabled";
+ };
+
sdmmc_ext: rksdmmc@ff5f0000 {
compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff5f0000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
+ max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
status = "disabled";
};
+ usb_host0_xhci: usb@ff600000 {
+ compatible = "rockchip,rk3328-xhci";
+ reg = <0x0 0xff600000 0x0 0x100000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ snps,dis-enblslpm-quirk;
+ snps,phyif-utmi-bits = <16>;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-u2-susphy-quirk;
+ status = "disabled";
+ };
+
gic: interrupt-controller@ffb70000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;