rockchip: jerry: Enable the Chrome OS EC
[oweals/u-boot.git] / arch / arm / dts / rk3288.dtsi
index 0f497099679470ea39078d6ca9e5b1ae550995b0..ac367f85b98807a7d5432ddadd81f1d9618ad73d 100644 (file)
                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
                interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
+               clock-frequency = <24000000>;
                clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";