ARM: DTS: Re-sync logicpd-som-lv with Linux 4.16-rc3

[oweals/u-boot.git] / arch / arm / dts / rk3288.dtsi

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 64aa07de36971189183c5c9cf64442109efe13b1..2c8a616782bce1aa7306661ec6ebb8e3ec5405e1 100644 (file)
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -167,7 +167,7 @@
 
        sdmmc: dwmmc@ff0c0000 {
                compatible = "rockchip,rk3288-dw-mshc";
-               clock-freq-min-max = <400000 150000000>;
+               max-frequency = <150000000>;
                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
                         <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -179,7 +179,7 @@
 
        sdio0: dwmmc@ff0d0000 {
                compatible = "rockchip,rk3288-dw-mshc";
-               clock-freq-min-max = <400000 150000000>;
+               max-frequency = <150000000>;
                clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
                         <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -191,7 +191,7 @@
 
        sdio1: dwmmc@ff0e0000 {
                compatible = "rockchip,rk3288-dw-mshc";
-               clock-freq-min-max = <400000 150000000>;
+               max-frequency = <150000000>;
                clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
                         <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -203,7 +203,7 @@
 
        emmc: dwmmc@ff0f0000 {
                compatible = "rockchip,rk3288-dw-mshc";
-               clock-freq-min-max = <400000 150000000>;
+               max-frequency = <150000000>;
                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                         <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -604,19 +604,16 @@
                u-boot,dm-pre-reloc;
                #clock-cells = <1>;
                #reset-cells = <1>;
-               assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
-                                 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+               assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
                                  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
                                  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
                                  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
                                  <&cru PCLK_PERI>;
-               assigned-clock-rates = <0>, <0>,
-                                      <594000000>, <400000000>,
+               assigned-clock-rates = <594000000>, <400000000>,
                                       <500000000>, <300000000>,
                                       <150000000>, <75000000>,
                                       <300000000>, <150000000>,
                                       <75000000>;
-               assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
        };
 
        grf: syscon@ff770000 {