ARM: dts: rmobile: Add soc label to Gen3
[oweals/u-boot.git] / arch / arm / dts / rk3288-veyron.dtsi
index a31e00eb5d2645491c9a11036be83700937e916c..92b68878fd0a52db482e824aca3cd7b359cc3833 100644 (file)
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Google Veyron (and derivatives) board device tree source
  *
  * Copyright 2014 Google, Inc
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <dt-bindings/clock/rockchip,rk808.h>
@@ -84,8 +83,6 @@
 
        gpio_keys: gpio-keys {
                compatible = "gpio-keys";
-               #address-cells = <1>;
-               #size-cells = <0>;
 
                pinctrl-names = "default";
                pinctrl-0 = <&pwr_key_h>;
                533000 1150000
                666000 1200000
        >;
-       rockchip,num-channels = <2>;
-       rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
-               0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
-               0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
-               0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
-               0x5 0x0>;
-       rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
-               0xa60 0x40 0x10 0x0>;
-       rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
-       rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 
 &efuse {
        clock-frequency = <400000>;
        i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
        i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
+       u-boot,dm-pre-reloc;
 
        rk808: pmic@1b {
                compatible = "rockchip,rk808";
                rockchip,system-power-controller;
                wakeup-source;
                #clock-cells = <1>;
+               u-boot,dm-pre-reloc;
 
                vcc1-supply = <&vcc33_sys>;
                vcc2-supply = <&vcc33_sys>;