Merge tag 'u-boot-rockchip-20200522' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / dts / rk322x.dtsi

diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index ddbe1137416ba08654e1d97a24835f926a6ea1c8..4a8be5dabbd88c4a0e2b0c23af63c6195fbfbb15 100644 (file)
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -207,7 +206,7 @@
                clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
                clock-names = "baudclk", "apb_pclk";
                pinctrl-names = "default";
-               pinctrl-0 = <&uart2_xfer>;
+               pinctrl-0 = <&uart21_xfer>;
                reg-shift = <2>;
                reg-io-width = <4>;
                status = "disabled";
@@ -388,6 +387,7 @@
        sdmmc: dwmmc@30000000 {
                compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x30000000 0x4000>;
+               max-frequency = <150000000>;
                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
                         <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
@@ -414,9 +414,8 @@
        emmc: dwmmc@30020000 {
                compatible = "rockchip,rk3288-dw-mshc";
                reg = <0x30020000 0x4000>;
+               max-frequency = <150000000>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-               clock-frequency = <37500000>;
-               max-frequency = <37500000>;
                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                         <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -749,7 +748,7 @@
 
                uart2 {
                        uart2_xfer: uart2-xfer {
-                               rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+                               rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>,
                                                <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
                        };
 
@@ -761,6 +760,13 @@
                                rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
                        };
                };
+
+               uart2-1 {
+                       uart21_xfer: uart21-xfer {
+                               rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 9 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
        };
 
        dmc: dmc@11200000 {