rockchip: rk3328: rock64 - fix gen3 SPL hang

[oweals/u-boot.git] / arch / arm / dts / rk3036.dtsi

diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi
index ecf54163185f1b7081718c1d03601f5e10e40b87..75588de4863992bb3b315420abca52eaec24f190 100644 (file)
--- a/arch/arm/dts/rk3036.dtsi
+++ b/arch/arm/dts/rk3036.dtsi
@@ -1,6 +1,4 @@
-/*
- * SPDX-License-Identifier:    GPL-2.0+
- */
+// SPDX-License-Identifier: GPL-2.0+
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -23,6 +21,7 @@
                serial1 = &uart1;
                serial2 = &uart2;
                mmc0 = &emmc;
+               mmc1 = &sdmmc;
        };
 
        memory {
@@ -243,7 +242,7 @@
        emmc: dwmmc@1021c000 {
                compatible = "rockchip,rk3288-dw-mshc";
                clock-frequency = <37500000>;
-               clock-freq-min-max = <400000 37500000>;
+               max-frequency = <37500000>;
                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
@@ -265,6 +264,18 @@
                pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
        };
 
+       sdmmc: dwmmc@10214000 {
+               compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x10214000 0x4000>;
+               clock-frequency = <37500000>;
+               max-frequency = <37500000>;
+               clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+               clock-names = "biu", "ciu";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3036-pinctrl";
                rockchip,grf = <&grf>;