Merge branch 'master' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / arch / arm / dts / r8a77995-draak.dts

diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts
index db2bed1751b8d308c814fc25c4e96000a819a6f1..a7dc11e36fd9d0cf9093f378d28c104486ac9b99 100644 (file)
--- a/arch/arm/dts/r8a77995-draak.dts
+++ b/arch/arm/dts/r8a77995-draak.dts
@@ -20,7 +20,7 @@
        };
 
        chosen {
-               bootargs = "ignore_loglevel";
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                stdout-path = "serial0:115200n8";
        };
 
@@ -168,7 +168,6 @@
        pinctrl-names = "default";
        renesas,no-ether-link;
        phy-handle = <&phy0>;
-       phy-mode = "rgmii-txid";
        status = "okay";
 
        phy0: ethernet-phy@0 {
@@ -179,6 +178,18 @@
        };
 };
 
+&can0 {
+       pinctrl-0 = <&can0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&can1 {
+       pinctrl-0 = <&can1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
 &du {
        pinctrl-0 = <&du_pins>;
        pinctrl-names = "default";
@@ -356,6 +367,13 @@
 };
 
 &lvds1 {
+       /*
+        * Even though the LVDS1 output is not connected, the encoder must be
+        * enabled to supply a pixel clock to the DU for the DPAD output when
+        * LVDS0 is in use.
+        */
+       status = "okay";
+
        clocks = <&cpg CPG_MOD 727>,
                 <&x12_clk>,
                 <&extal_clk>;
@@ -375,6 +393,16 @@
                };
        };
 
+       can0_pins: can0 {
+               groups = "can0_data_a";
+               function = "can0";
+       };
+
+       can1_pins: can1 {
+               groups = "can1_data_a";
+               function = "can1";
+       };
+
        du_pins: du {
                groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
                function = "du";