ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / dts / mt7623.dtsi

diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 448d1d73810e549bc7c02fb6cadc7d759b315187..0452889ef800a7387f8513820e38e77715ceaf34 100644 (file)
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -9,8 +9,9 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt7623-power.h>
-#include <dt-bindings/reset/mtk-reset.h>
+#include <dt-bindings/reset/mt7623-reset.h>
 #include "skeleton.dtsi"
 
 / {
@@ -100,21 +101,18 @@
                compatible = "mediatek,mt7623-topckgen";
                reg = <0x10000000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        infracfg: syscon@10001000 {
                compatible = "mediatek,mt7623-infracfg", "syscon";
                reg = <0x10001000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        pericfg: syscon@10003000 {
                compatible = "mediatek,mt7623-pericfg", "syscon";
                reg = <0x10003000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        pinctrl: pinctrl@10005000 {
@@ -154,7 +152,6 @@
                interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
                clocks = <&system_clk>;
                clock-names = "system-clk";
-               u-boot,dm-pre-reloc;
        };
 
        sysirq: interrupt-controller@10200100 {
@@ -169,7 +166,6 @@
                compatible = "mediatek,mt7623-apmixedsys";
                reg = <0x10209000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        gic: interrupt-controller@10211000 {
@@ -214,7 +210,6 @@
                         <&pericfg CLK_PERI_UART2>;
                clock-names = "baud", "bus";
                status = "disabled";
-               u-boot,dm-pre-reloc;
        };
 
        uart3: serial@11005000 {
@@ -248,6 +243,140 @@
                status = "disabled";
        };
 
+       hifsys: syscon@1a000000 {
+               compatible = "mediatek,mt7623-hifsys", "syscon";
+               reg = <0x1a000000 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       pcie: pcie@1a140000 {
+               compatible = "mediatek,mt7623-pcie";
+               device_type = "pci";
+               reg = <0x1a140000 0x1000>, /* PCIe shared registers */
+                     <0x1a142000 0x1000>, /* Port0 registers */
+                     <0x1a143000 0x1000>, /* Port1 registers */
+                     <0x1a144000 0x1000>; /* Port2 registers */
+               reg-names = "subsys", "port0", "port1", "port2";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0xf800 0 0 0>;
+               interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+                               <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+                               <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+                        <&hifsys CLK_HIFSYS_PCIE0>,
+                        <&hifsys CLK_HIFSYS_PCIE1>,
+                        <&hifsys CLK_HIFSYS_PCIE2>;
+               clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+               resets = <&hifsys HIFSYS_PCIE0_RST>,
+                        <&hifsys HIFSYS_PCIE1_RST>,
+                        <&hifsys HIFSYS_PCIE2_RST>;
+               reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+               phys = <&pcie0_port PHY_TYPE_PCIE>,
+                      <&pcie1_port PHY_TYPE_PCIE>,
+                      <&u3port1 PHY_TYPE_PCIE>;
+               phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+               power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+               bus-range = <0x00 0xff>;
+               status = "disabled";
+               ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000
+                         0x83000000 0 0x60000000 0x60000000 0 0x10000000>;
+
+               pcie@0,0 {
+                       reg = <0x0000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       status = "disabled";
+               };
+
+               pcie@1,0 {
+                       reg = <0x0800 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       status = "disabled";
+               };
+
+               pcie@2,0 {
+                       reg = <0x1000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+                       ranges;
+                       status = "disabled";
+               };
+       };
+
+       pcie0_phy: pcie-phy@1a149000 {
+               compatible = "mediatek,generic-tphy-v1";
+               reg = <0x1a149000 0x0700>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               status = "disabled";
+
+               pcie0_port: pcie-phy@1a149900 {
+                       reg = <0x1a149900 0x0700>;
+                       clocks = <&clk26m>;
+                       clock-names = "ref";
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+       };
+
+       pcie1_phy: pcie-phy@1a14a000 {
+               compatible = "mediatek,generic-tphy-v1";
+               reg = <0x1a14a000 0x0700>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               status = "disabled";
+
+               pcie1_port: pcie-phy@1a14a900 {
+                       reg = <0x1a14a900 0x0700>;
+                       clocks = <&clk26m>;
+                       clock-names = "ref";
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+       };
+
+       u3phy2: usb-phy@1a244000 {
+               compatible = "mediatek,generic-tphy-v1";
+               reg = <0x1a244000 0x0700>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               status = "disabled";
+
+               u2port1: usb-phy@1a244800 {
+                       reg = <0x1a244800 0x0100>;
+                       clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+                       clock-names = "ref";
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+
+               u3port1: usb-phy@1a244900 {
+                       reg = <0x1a244900 0x0700>;
+                       clocks = <&clk26m>;
+                       clock-names = "ref";
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+       };
+
        ethsys: syscon@1b000000 {
                compatible = "mediatek,mt7623-ethsys", "syscon";
                reg = <0x1b000000 0x1000>;
@@ -271,4 +400,21 @@
                mediatek,ethsys = <&ethsys>;
                status = "disabled";
        };
+
+       pwm: pwm@11006000 {
+               compatible = "mediatek,mt7623-pwm";
+               reg = <0x11006000 0x1000>;
+               #clock-cells = <1>;
+               #pwm-cells = <2>;
+               clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                        <&pericfg CLK_PERI_PWM>,
+                        <&pericfg CLK_PERI_PWM1>,
+                        <&pericfg CLK_PERI_PWM2>,
+                        <&pericfg CLK_PERI_PWM3>,
+                        <&pericfg CLK_PERI_PWM4>,
+                        <&pericfg CLK_PERI_PWM5>;
+               clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
+                             "pwm5";
+               status = "disabled";
+       };
 };