Merge branch 'master' of git://git.denx.de/u-boot
[oweals/u-boot.git] / arch / arm / dts / meson-gxm.dtsi
index 247888d68a3aabe06e8841a8d93cbfe8afe12960..b6f89f108e2829ec94e734eff0f130c74f2d2d68 100644 (file)
 
                cpu4: cpu@100 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
+                       #cooling-cells = <2>;
                };
 
                cpu5: cpu@101 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
+                       #cooling-cells = <2>;
                };
 
                cpu6: cpu@102 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
+                       #cooling-cells = <2>;
                };
 
                cpu7: cpu@103 {
                        device_type = "cpu";
-                       compatible = "arm,cortex-a53", "arm,armv8";
+                       compatible = "arm,cortex-a53";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
+                       #cooling-cells = <2>;
                };
        };
 };
                reset-names = "phy";
                status = "okay";
        };
+
+       mali: gpu@c0000 {
+               compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
+               reg = <0x0 0xc0000 0x0 0x40000>;
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "job", "mmu", "gpu";
+               clocks = <&clkc CLKID_MALI>;
+               resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
+
+               /*
+                * Mali clocking is provided by two identical clock paths
+                * MALI_0 and MALI_1 muxed to a single clock by a glitch
+                * free mux to safely change frequency while running.
+                */
+               assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+                                 <&clkc CLKID_MALI_0>,
+                                 <&clkc CLKID_MALI>; /* Glitch free mux */
+               assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                                        <0>, /* Do Nothing */
+                                        <&clkc CLKID_MALI_0>;
+               assigned-clock-rates = <0>, /* Do Nothing */
+                                      <666666666>,
+                                      <0>; /* Do Nothing */
+       };
 };
 
 &clkc_AO {
        compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
 };
 
+&cpu_cooling_maps {
+       map0 {
+               cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+       };
+
+       map1 {
+               cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+       };
+};
+
 &saradc {
        compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
 };
 &dwc3 {
        phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
 };
+
+&vdec {
+       compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec";
+};