+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gx.dtsi"
};
};
-ðmac {
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
-};
-
&aobus {
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl";
function = "spdif_out_ao";
};
};
+
+ ao_cec_pins: ao_cec {
+ mux {
+ groups = "ao_cec";
+ function = "cec_ao";
+ };
+ };
+
+ ee_cec_pins: ee_cec {
+ mux {
+ groups = "ee_cec";
+ function = "cec_ao";
+ };
+ };
};
};
+&apb {
+ mali: gpu@c0000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0xc0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_GP0_PLL>,
+ <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <0>, /* Do Nothing */
+ <&clkc CLKID_GP0_PLL>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <744000000>,
+ <0>, /* Do Nothing */
+ <744000000>,
+ <0>; /* Do Nothing */
+ };
+};
+
+&cbus {
+ spifc: spi@8c80 {
+ compatible = "amlogic,meson-gxbb-spifc";
+ reg = <0x0 0x08c80 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_SPI>;
+ status = "disabled";
+ };
+};
+
+&cec_AO {
+ clocks = <&clkc_AO CLKID_AO_CEC_32K>;
+ clock-names = "core";
+};
+
+&clkc_AO {
+ compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
+};
+
+ðmac {
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+};
+
+&gpio_intc {
+ compatible = "amlogic,meson-gpio-intc",
+ "amlogic,meson-gxbb-gpio-intc";
+ status = "okay";
+};
+
+&hdmi_tx {
+ compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
+ resets = <&reset RESET_HDMITX_CAPB3>,
+ <&reset RESET_HDMI_SYSTEM_RESET>,
+ <&reset RESET_HDMI_TX>;
+ reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+ clocks = <&clkc CLKID_HDMI_PCLK>,
+ <&clkc CLKID_CLK81>,
+ <&clkc CLKID_GCLK_VENCI_INT0>;
+ clock-names = "isfr", "iahb", "venci";
+};
+
+&sysctrl {
+ clkc: clock-controller {
+ compatible = "amlogic,gxbb-clkc";
+ #clock-cells = <1>;
+ };
+};
+
+&hwrng {
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+};
+
+&i2c_A {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_AO {
+ clocks = <&clkc CLKID_AO_I2C>;
+};
+
+&i2c_B {
+ clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_C {
+ clocks = <&clkc CLKID_I2C>;
+};
+
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
- <0x0 0x00120 0x0 0x14>,
+ <0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl_periphs 0 14 120>;
+ gpio-ranges = <&pinctrl_periphs 0 0 119>;
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d07",
"emmc_cmd",
- "emmc_clk",
- "emmc_ds";
+ "emmc_clk";
function = "emmc";
};
};
+ emmc_ds_pins: emmc-ds {
+ mux {
+ groups = "emmc_ds";
+ function = "emmc";
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "BOOT_8";
+ function = "gpio_periphs";
+ };
+ cfg-pull-down {
+ pins = "BOOT_8";
+ bias-pull-down;
+ };
+ };
+
nor_pins: nor {
mux {
groups = "nor_d",
};
};
+ spi_pins: spi-pins {
+ mux {
+ groups = "spi_miso",
+ "spi_mosi",
+ "spi_sclk";
+ function = "spi";
+ };
+ };
+
+ spi_ss0_pins: spi-ss0 {
+ mux {
+ groups = "spi_ss0";
+ function = "spi";
+ };
+ };
+
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
};
};
+ sdcard_clk_gate_pins: sdcard_clk_gate {
+ mux {
+ groups = "CARD_2";
+ function = "gpio_periphs";
+ };
+ cfg-pull-down {
+ pins = "CARD_2";
+ bias-pull-down;
+ };
+ };
+
sdio_pins: sdio {
mux {
groups = "sdio_d0",
};
};
+ sdio_clk_gate_pins: sdio_clk_gate {
+ mux {
+ groups = "GPIOX_4";
+ function = "gpio_periphs";
+ };
+ cfg-pull-down {
+ pins = "GPIOX_4";
+ bias-pull-down;
+ };
+ };
+
sdio_irq_pins: sdio_irq {
mux {
groups = "sdio_irq";
};
};
-&hiubus {
- clkc: clock-controller@0 {
- compatible = "amlogic,gxbb-clkc";
- #clock-cells = <1>;
- reg = <0x0 0x0 0x0 0x3db>;
- };
-};
-
-&apb {
- mali: gpu@c0000 {
- compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
- reg = <0x0 0xc0000 0x0 0x40000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp", "gpmmu", "pp", "pmu",
- "pp0", "ppmmu0", "pp1", "ppmmu1",
- "pp2", "ppmmu2";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- clock-names = "bus", "core";
-
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
- <0>; /* Do Nothing */
- };
-};
-
-&i2c_A {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_AO {
- clocks = <&clkc CLKID_AO_I2C>;
-};
-
-&i2c_B {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_C {
- clocks = <&clkc CLKID_I2C>;
+&pwrc_vpu {
+ resets = <&reset RESET_VIU>,
+ <&reset RESET_VENC>,
+ <&reset RESET_VCBUS>,
+ <&reset RESET_BT656>,
+ <&reset RESET_DVIN_RESET>,
+ <&reset RESET_RDMA>,
+ <&reset RESET_VENCI>,
+ <&reset RESET_VENCP>,
+ <&reset RESET_VDAC>,
+ <&reset RESET_VDI6>,
+ <&reset RESET_VENCL>,
+ <&reset RESET_VID_LOCK>;
+ clocks = <&clkc CLKID_VPU>,
+ <&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ /*
+ * VPU clocking is provided by two identical clock paths
+ * VPU_0 and VPU_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ * Same for VAPB but with a final gate after the glitch free mux.
+ */
+ assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_VPU>, /* Glitch free mux */
+ <&clkc CLKID_VAPB_0_SEL>,
+ <&clkc CLKID_VAPB_0>,
+ <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_VPU_0>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_VAPB_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <666666666>,
+ <0>, /* Do Nothing */
+ <0>, /* Do Nothing */
+ <250000000>,
+ <0>; /* Do Nothing */
};
&saradc {
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
<&clkc CLKID_SAR_ADC>,
- <&clkc CLKID_SANA>,
<&clkc CLKID_SAR_ADC_CLK>,
<&clkc CLKID_SAR_ADC_SEL>;
- clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ clock-names = "clkin", "core", "adc_clk", "adc_sel";
};
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
- <&xtal>,
+ <&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_A>;
};
&sd_emmc_b {
clocks = <&clkc CLKID_SD_EMMC_B>,
- <&xtal>,
+ <&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_B>;
};
&sd_emmc_c {
clocks = <&clkc CLKID_SD_EMMC_C>,
- <&xtal>,
+ <&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ resets = <&reset RESET_SD_EMMC_C>;
+};
+
+&spicc {
+ clocks = <&clkc CLKID_SPICC>;
+ clock-names = "core";
+ resets = <&reset RESET_PERIPHS_SPICC>;
+ num-cs = <1>;
};
&spifc {
clocks = <&clkc CLKID_SPI>;
};
-&vpu {
- compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
+&uart_A {
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
};
-&hwrng {
- clocks = <&clkc CLKID_RNG0>;
- clock-names = "core";
+&uart_AO {
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
};
-&hdmi_tx {
- compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
- resets = <&reset RESET_HDMITX_CAPB3>,
- <&reset RESET_HDMI_SYSTEM_RESET>,
- <&reset RESET_HDMI_TX>;
- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
- <&clkc CLKID_GCLK_VENCI_INT0>;
- clock-names = "isfr", "iahb", "venci";
+&uart_AO_B {
+ clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_C {
+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+};
+
+&vpu {
+ compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
+ power-domains = <&pwrc_vpu>;
};
projects / oweals / u-boot.git / blobdiff