arm64: dts: meson: sync dt and bindings from v5.7-rc1
[oweals/u-boot.git] / arch / arm / dts / meson-g12-common.dtsi
index abe04f4ad7d873ba95f41e3b2e7b2b767f65aab9..0882ea215b88f3a600f2b581029b7c852bf92e06 100644 (file)
                                                };
                                        };
 
-                                       emmc_pins: emmc {
+                                       emmc_ctrl_pins: emmc-ctrl {
                                                mux-0 {
-                                                       groups = "emmc_nand_d0",
-                                                                "emmc_nand_d1",
-                                                                "emmc_nand_d2",
-                                                                "emmc_nand_d3",
-                                                                "emmc_nand_d4",
-                                                                "emmc_nand_d5",
-                                                                "emmc_nand_d6",
-                                                                "emmc_nand_d7",
-                                                                "emmc_cmd";
+                                                       groups = "emmc_cmd";
                                                        function = "emmc";
                                                        bias-pull-up;
                                                        drive-strength-microamp = <4000>;
                                                };
                                        };
 
+                                       emmc_data_4b_pins: emmc-data-4b {
+                                               mux-0 {
+                                                       groups = "emmc_nand_d0",
+                                                                "emmc_nand_d1",
+                                                                "emmc_nand_d2",
+                                                                "emmc_nand_d3";
+                                                       function = "emmc";
+                                                       bias-pull-up;
+                                                       drive-strength-microamp = <4000>;
+                                               };
+                                       };
+
+                                       emmc_data_8b_pins: emmc-data-8b {
+                                               mux-0 {
+                                                       groups = "emmc_nand_d0",
+                                                                "emmc_nand_d1",
+                                                                "emmc_nand_d2",
+                                                                "emmc_nand_d3",
+                                                                "emmc_nand_d4",
+                                                                "emmc_nand_d5",
+                                                                "emmc_nand_d6",
+                                                                "emmc_nand_d7";
+                                                       function = "emmc";
+                                                       bias-pull-up;
+                                                       drive-strength-microamp = <4000>;
+                                               };
+                                       };
+
                                        emmc_ds_pins: emmc-ds {
                                                mux {
                                                        groups = "emmc_nand_ds";
                                                };
                                        };
 
+                                       nor_pins: nor {
+                                               mux {
+                                                       groups = "nor_d",
+                                                              "nor_q",
+                                                              "nor_c",
+                                                              "nor_cs";
+                                                       function = "nor";
+                                                       bias-disable;
+                                               };
+                                       };
+
                                        pdm_din0_a_pins: pdm-din0-a {
                                                mux {
                                                        groups = "pdm_din0_a";
                                                };
                                        };
 
+                                       spicc0_x_pins: spicc0-x {
+                                               mux {
+                                                       groups = "spi0_mosi_x",
+                                                              "spi0_miso_x",
+                                                              "spi0_clk_x";
+                                                       function = "spi0";
+                                                       drive-strength-microamp = <4000>;
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       spicc0_ss0_x_pins: spicc0-ss0-x {
+                                               mux {
+                                                       groups = "spi0_ss0_x";
+                                                       function = "spi0";
+                                                       drive-strength-microamp = <4000>;
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       spicc0_c_pins: spicc0-c {
+                                               mux {
+                                                       groups = "spi0_mosi_c",
+                                                              "spi0_miso_c",
+                                                              "spi0_ss0_c",
+                                                              "spi0_clk_c";
+                                                       function = "spi0";
+                                                       drive-strength-microamp = <4000>;
+                                                       bias-disable;
+                                               };
+                                       };
+
+                                       spicc1_pins: spicc1 {
+                                               mux {
+                                                       groups = "spi1_mosi",
+                                                              "spi1_miso",
+                                                              "spi1_clk";
+                                                       function = "spi1";
+                                                       drive-strength-microamp = <4000>;
+                                               };
+                                       };
+
+                                       spicc1_ss0_pins: spicc1-ss0 {
+                                               mux {
+                                                       groups = "spi1_ss0";
+                                                       function = "spi1";
+                                                       drive-strength-microamp = <4000>;
+                                                       bias-disable;
+                                               };
+                                       };
+
                                        tdm_a_din0_pins: tdm-a-din0 {
                                                mux {
                                                        groups = "tdm_a_din0";
                                amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
                        };
 
+                       spicc0: spi@13000 {
+                               compatible = "amlogic,meson-g12a-spicc";
+                               reg = <0x0 0x13000 0x0 0x44>;
+                               interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clkc CLKID_SPICC0>,
+                                        <&clkc CLKID_SPICC0_SCLK>;
+                               clock-names = "core", "pclk";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spicc1: spi@15000 {
+                               compatible = "amlogic,meson-g12a-spicc";
+                               reg = <0x0 0x15000 0x0 0x44>;
+                               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clkc CLKID_SPICC1>,
+                                        <&clkc CLKID_SPICC1_SCLK>;
+                               clock-names = "core", "pclk";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spifc: spi@14000 {
+                               compatible = "amlogic,meson-gxbb-spifc";
+                               status = "disabled";
+                               reg = <0x0 0x14000 0x0 0x80>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               clocks = <&clkc CLKID_CLK81>;
+                       };
+
                        pwm_ef: pwm@19000 {
                                compatible = "amlogic,meson-g12a-ee-pwm";
                                reg = <0x0 0x19000 0x0 0x20>;
                                dr_mode = "host";
                                snps,dis_u2_susphy_quirk;
                                snps,quirk-frame-length-adjustment;
+                               snps,parkmode-disable-ss-quirk;
                        };
                };