+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale ls1021a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include "skeleton.dtsi"
sdhci,auto-cmd12;
big-endian;
bus-width = <4>;
- status = "disabled";
};
scfg: scfg@1570000 {
};
qspi: quadspi@1550000 {
- compatible = "fsl,vf610-qspi";
+ compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1550000 0x10000>,
- <0x40000000 0x4000000>;
- num-cs = <2>;
- big-endian;
+ <0x40000000 0x1000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
status = "disabled";
};
compatible = "fsl,16550-FIFO64", "ns16550a";
reg = <0x21c0500 0x100>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <0>;
fifo-size = <15>;
status = "disabled";
};
compatible = "fsl,16550-FIFO64", "ns16550a";
reg = <0x21c0600 0x100>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <0>;
fifo-size = <15>;
status = "disabled";
};
compatible = "fsl,16550-FIFO64", "ns16550a";
reg = <0x21d0500 0x100>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <0>;
fifo-size = <15>;
status = "disabled";
};
compatible = "fsl,16550-FIFO64", "ns16550a";
reg = <0x21d0600 0x100>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <0>;
fifo-size = <15>;
status = "disabled";
};
<&platform_clk 1>;
};
+ enet0: ethernet@2d10000 {
+ compatible = "fsl,etsec2";
+ reg = <0x2d10000 0x1000>;
+ status = "disabled";
+ };
+
+ enet1: ethernet@2d50000 {
+ compatible = "fsl,etsec2";
+ reg = <0x2d50000 0x1000>;
+ status = "disabled";
+ };
+
+ enet2: ethernet@2d90000 {
+ compatible = "fsl,etsec2";
+ reg = <0x2d90000 0x1000>;
+ status = "disabled";
+ };
+
mdio0: mdio@2d24000 {
- compatible = "gianfar";
- device_type = "mdio";
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x2d24000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio1: mdio@2d64000 {
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x2d64000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x2d24000 0x4000>;
};
usb@8600000 {
};
usb3@3100000 {
- compatible = "snps,dwc3";
+ compatible = "fsl,layerscape-dwc3";
reg = <0x3100000 0x10000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
};
+
+ pcie@3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x03400000 0x20000 /* dbi registers */
+ 0x01570000 0x10000 /* pf controls registers */
+ 0x24000000 0x20000>; /* configuration space */
+ reg-names = "dbi", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x03500000 0x10000 /* dbi registers */
+ 0x01570000 0x10000 /* pf controls registers */
+ 0x34000000 0x20000>; /* configuration space */
+ reg-names = "dbi", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1021a-ahci";
+ reg = <0x3200000 0x10000 0x20220520 0x4>;
+ reg-names = "sata-base", "ecc-addr";
+ interrupts = <0 101 4>;
+ status = "disabled";
+ };
};
};