model = "LS1021A TWR Board";
aliases {
- enet2_rgmii_phy = &rgmii_phy1;
- enet0_sgmii_phy = &sgmii_phy2;
- enet1_sgmii_phy = &sgmii_phy0;
+ enet2-rgmii-phy = &rgmii_phy1;
+ enet0-sgmii-phy = &sgmii_phy2;
+ enet1-sgmii-phy = &sgmii_phy0;
spi0 = &qspi;
spi1 = &dspi1;
};
qflash0: n25q128a13@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "spi-flash";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
dspiflash: at26df081a@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "spi-flash";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <16000000>;
spi-cpol;
spi-cpha;
};
};
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
sgmii_phy0: ethernet-phy@0 {
reg = <0x0>;
};
+
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
+
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
+
+ /* SGMII PCS for enet0 */
+ tbi0: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&mdio1 {
+ /* SGMII PCS for enet1 */
tbi1: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";