ARM: dts: stm32mp15: use DDR3 files generated by STM32CubeMX

[oweals/u-boot.git] / arch / arm / dts / ls1021a-twr.dtsi

diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index 928e1002585c637dd1c51ef12514c89b84fb8f55..27c96f95400ae4c586ffabc977c7ad9626093d0d 100644 (file)
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -30,7 +30,7 @@
        qflash0: n25q128a13@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "spi-flash";
+               compatible = "jedec,spi-nor";
                spi-max-frequency = <20000000>;
                reg = <0>;
        };
@@ -43,7 +43,7 @@
        dspiflash: at26df081a@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "spi-flash";
+               compatible = "jedec,spi-nor";
                spi-max-frequency = <16000000>;
                spi-cpol;
                spi-cpha;
@@ -51,6 +51,26 @@
        };
 };
 
+&enet0 {
+       tbi-handle = <&tbi0>;
+       phy-handle = <&sgmii_phy2>;
+       phy-connection-type = "sgmii";
+       status = "okay";
+};
+
+&enet1 {
+       tbi-handle = <&tbi1>;
+       phy-handle = <&sgmii_phy0>;
+       phy-connection-type = "sgmii";
+       status = "okay";
+};
+
+&enet2 {
+       phy-handle = <&rgmii_phy1>;
+       phy-connection-type = "rgmii-id";
+       status = "okay";
+};
+
 &i2c0 {
        status = "okay";
 };
@@ -84,12 +104,24 @@
        sgmii_phy0: ethernet-phy@0 {
                reg = <0x0>;
        };
+
        rgmii_phy1: ethernet-phy@1 {
                reg = <0x1>;
        };
+
        sgmii_phy2: ethernet-phy@2 {
                reg = <0x2>;
        };
+
+       /* SGMII PCS for enet0 */
+       tbi0: tbi-phy@1f {
+               reg = <0x1f>;
+               device_type = "tbi-phy";
+       };
+};
+
+&mdio1 {
+       /* SGMII PCS for enet1 */
        tbi1: tbi-phy@1f {
                reg = <0x1f>;
                device_type = "tbi-phy";