arm: dts: ls1028a: add lpuart nodes

[oweals/u-boot.git] / arch / arm / dts / k3-j721e-main.dtsi

diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index 5083a0c3aef05cff2d197db2e98e75f0a005f292..1433932e7f383f9e64b8f7457f7ddfa0147eefe9 100644 (file)
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -200,6 +200,28 @@
                clock-names = "fclk";
        };
 
+       main_gpio0: gpio@600000 {
+               compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00600000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
+                            <105 1 IRQ_TYPE_EDGE_RISING>,
+                            <105 2 IRQ_TYPE_EDGE_RISING>,
+                            <105 3 IRQ_TYPE_EDGE_RISING>,
+                            <105 4 IRQ_TYPE_EDGE_RISING>,
+                            <105 5 IRQ_TYPE_EDGE_RISING>,
+                            <105 6 IRQ_TYPE_EDGE_RISING>,
+                            <105 7 IRQ_TYPE_EDGE_RISING>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <128>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 105 0>;
+               clock-names = "gpio";
+       };
+
        main_sdhci0: sdhci@4f80000 {
                compatible = "ti,j721e-sdhci-8bit";
                reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
@@ -210,9 +232,14 @@
                assigned-clocks = <&k3_clks 91 1>;
                assigned-clock-parents = <&k3_clks 91 2>;
                bus-width = <8>;
-               ti,otap-del-sel = <0x2>;
                ti,trm-icp = <0x8>;
                dma-coherent;
+               mmc-ddr-1_8v;
+               ti,otap-del-sel-legacy = <0x0>;
+               ti,otap-del-sel-mmc-hs = <0x0>;
+               ti,otap-del-sel-ddr52 = <0x5>;
+               ti,otap-del-sel-hs200 = <0x6>;
+               ti,otap-del-sel-hs400 = <0x0>;
        };
 
        main_sdhci1: sdhci@4fb0000 {
@@ -224,7 +251,13 @@
                clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
                assigned-clocks = <&k3_clks 92 0>;
                assigned-clock-parents = <&k3_clks 92 1>;
-               ti,otap-del-sel = <0x2>;
+               ti,otap-del-sel-legacy = <0x0>;
+               ti,otap-del-sel-sd-hs = <0xf>;
+               ti,otap-del-sel-sdr12 = <0xf>;
+               ti,otap-del-sel-sdr25 = <0xf>;
+               ti,otap-del-sel-sdr50 = <0xc>;
+               ti,otap-del-sel-sdr104 = <0x5>;
+               ti,otap-del-sel-ddr50 = <0xc>;
                ti,trm-icp = <0x8>;
                dma-coherent;
        };
@@ -433,4 +466,81 @@
                        dma-coherent;
                };
        };
+
+       main_i2c0: i2c@2000000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x0 0x2000000 0x0 0x100>;
+               interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 187 0>;
+               power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c1: i2c@2010000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x0 0x2010000 0x0 0x100>;
+               interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 188 0>;
+               power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c2: i2c@2020000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x0 0x2020000 0x0 0x100>;
+               interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 189 0>;
+               power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c3: i2c@2030000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x0 0x2030000 0x0 0x100>;
+               interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 190 0>;
+               power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c4: i2c@2040000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x0 0x2040000 0x0 0x100>;
+               interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 191 0>;
+               power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c5: i2c@2050000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x0 0x2050000 0x0 0x100>;
+               interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 192 0>;
+               power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c6: i2c@2060000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x0 0x2060000 0x0 0x100>;
+               interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 193 0>;
+               power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+       };
 };