arm: dts: rockchip: px30: add and enable rng node

[oweals/u-boot.git] / arch / arm / dts / imx6ul-isiot.dtsi

diff --git a/arch/arm/dts/imx6ul-isiot.dtsi b/arch/arm/dts/imx6ul-isiot.dtsi
index 9a3c35c56a0a93e571dcc12288748c6fd3221c1c..4ed7313683d9e990b614053032bebd77274e25c4 100644 (file)
--- a/arch/arm/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/dts/imx6ul-isiot.dtsi
@@ -42,7 +42,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include "imx6ul.dtsi"
 
 / {
        memory {
@@ -90,6 +89,15 @@
        status = "okay";
 };
 
+&usdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+       bus-width = <8>;
+       no-1-8-v;
+       status = "disabled";
+};
+
 &iomuxc {
        pinctrl_enet1: enet1grp {
                fsl,pins = <
@@ -137,4 +145,21 @@
                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
                >;
        };
+
+       pinctrl_usdhc2: usdhc2grp {
+               u-boot,dm-spl;
+               fsl,pins = <
+                       MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
+                       MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
+                       MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
+                       MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
+                       MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
+                       MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
+                       MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
+                       MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
+                       MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
+                       MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
+                       MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
+               >;
+       };
 };