Merge branch 'master' of git://git.denx.de/u-boot

[oweals/u-boot.git] / arch / arm / dts / imx6ul-isiot.dtsi

diff --git a/arch/arm/dts/imx6ul-isiot.dtsi b/arch/arm/dts/imx6ul-isiot.dtsi
index 6108a1af5e772799a53fb108569af8ce56e187f1..4ed7313683d9e990b614053032bebd77274e25c4 100644 (file)
--- a/arch/arm/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/dts/imx6ul-isiot.dtsi
@@ -40,11 +40,8 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/dts-v1/;
-
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include "imx6ul.dtsi"
 
 / {
        memory {
@@ -56,6 +53,27 @@
        };
 };
 
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>;
+       phy-mode = "rmii";
+       status = "okay";
+};
+
+&i2c1 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+};
+
+&i2c2 {
+       clock_frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+};
+
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -71,7 +89,45 @@
        status = "okay";
 };
 
+&usdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+       bus-width = <8>;
+       no-1-8-v;
+       status = "disabled";
+};
+
 &iomuxc {
+       pinctrl_enet1: enet1grp {
+               fsl,pins = <
+                       MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO    0x1b0b0
+                       MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC     0x1b0b0
+                       MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                       MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                       MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                       MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                       MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+                       MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10       0x1b0b0
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+                       MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+                       fsl,pins = <
+                       MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+                       MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
@@ -89,4 +145,21 @@
                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
                >;
        };
+
+       pinctrl_usdhc2: usdhc2grp {
+               u-boot,dm-spl;
+               fsl,pins = <
+                       MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
+                       MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
+                       MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
+                       MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
+                       MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
+                       MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
+                       MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
+                       MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
+                       MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
+                       MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
+                       MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
+               >;
+       };
 };