ARM: dts: i.MX6QDL: icore-rqs: Fix eMMC detection during SPL

[oweals/u-boot.git] / arch / arm / dts / imx6qdl-icore.dtsi

diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
index f424cd5a1afffa38ebe5b32458435978295ea26f..913dc99c54f297546e317cc5befa7987e6ac530b 100644 (file)
--- a/arch/arm/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -44,6 +44,10 @@
 #include <dt-bindings/input/input.h>
 
 / {
+       aliases {
+               mmc1 = &usdhc3;
+       };
+
        memory {
                reg = <0x10000000 0x80000000>;
        };
@@ -75,6 +79,14 @@
        assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
 };
 
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet>;
+       phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+       phy-mode = "rmii";
+       status = "okay";
+};
+
 &gpmi {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -110,6 +122,7 @@
 };
 
 &usdhc1 {
+       u-boot,dm-spl;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc1>;
        cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -117,7 +130,31 @@
        status = "okay";
 };
 
+&usdhc3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       no-1-8-v;
+       non-removable;
+       status = "disabled";
+};
+
 &iomuxc {
+       pinctrl_enet: enetgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
+                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b0b1
+                       MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
+                       MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
+                       MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
+                       MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
+                       MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
+                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                       MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
+                       MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
+               >;
+       };
+
        pinctrl_flexcan1: flexcan1grp {
                fsl,pins = <
                        MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
@@ -184,6 +221,7 @@
        };
 
        pinctrl_usdhc1: usdhc1grp {
+               u-boot,dm-spl;
                fsl,pins = <
                        MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
                        MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
@@ -193,4 +231,20 @@
                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
                >;
        };
+
+       pinctrl_usdhc3: usdhc3grp {
+               u-boot,dm-spl;
+               fsl,pins = <
+                       MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+                       MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                       MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+                       MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+                       MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+                       MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+               >;
+       };
 };