rockchip: rk3328: Add support for ROC-RK3328-CC board

[oweals/u-boot.git] / arch / arm / dts / fsl-ls1088a-qds.dts

diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts
index 225c7c53c752997ac0c18568863fe0da9008bd15..f07d0c6f2748939ffc161d9fab0b761510f79e86 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a-qds.dts
+++ b/arch/arm/dts/fsl-ls1088a-qds.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
  * NXP ls1088a QDS board device tree source
  *
  * Copyright 2017 NXP
- *
- * SPDX-License-Identifier:    GPL-2.0+        X11
  */
 
 /dts-v1/;
@@ -19,6 +18,66 @@
        };
 };
 
+&i2c0 {
+       status = "okay";
+       u-boot,dm-pre-reloc;
+
+       i2c-mux@77 {
+               compatible = "nxp,pca9547";
+               reg = <0x77>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               i2c@3 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x3>;
+
+                       rtc@51 {
+                               compatible = "pcf2127-rtc";
+                               reg = <0x51>;
+                       };
+               };
+       };
+};
+
+&ifc {
+       #address-cells = <2>;
+       #size-cells = <1>;
+       /* NOR, NAND Flashes and FPGA on board */
+       ranges = <0 0 0x5 0x80000000 0x08000000
+                       2 0 0x5 0x30000000 0x00010000
+                       3 0 0x5 0x20000000 0x00010000>;
+       status = "okay";
+
+       nor@0,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0x0 0x0 0x8000000>;
+               bank-width = <2>;
+               device-width = <1>;
+       };
+
+       nand@2,0 {
+               compatible = "fsl,ifc-nand";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x1 0x0 0x10000>;
+       };
+
+       fpga: board-control@3,0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus", "fsl,ls1088aqds-fpga",
+                               "fsl,fpga-qixis";
+               reg = <0x2 0x0 0x0000100>;
+               bank-width = <1>;
+               device-width = <1>;
+               ranges = <0 2 0 0x100>;
+       };
+};
+
 &dspi {
        bus-num = <0>;
        status = "okay";
@@ -26,7 +85,7 @@
        dflash0: n25q128a {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "spi-flash";
+               compatible = "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <1000000>; /* input clock */
        };
@@ -34,7 +93,7 @@
        dflash1: sst25wf040b {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "spi-flash";
+               compatible = "jedec,spi-nor";
                spi-max-frequency = <3500000>;
                reg = <1>;
        };
@@ -42,7 +101,7 @@
        dflash2: en25s64 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "spi-flash";
+               compatible = "jedec,spi-nor";
                spi-max-frequency = <3500000>;
                reg = <2>;
        };
@@ -55,7 +114,7 @@
        qflash0: s25fs512s@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "spi-flash";
+               compatible = "jedec,spi-nor";
                spi-max-frequency = <50000000>;
                reg = <0>;
        };
@@ -63,8 +122,12 @@
        qflash1: s25fs512s@1 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "spi-flash";
+               compatible = "jedec,spi-nor";
                spi-max-frequency = <50000000>;
                reg = <1>;
         };
 };
+
+&sata {
+       status = "okay";
+};