sunxi: Add A20-SOM204-EVB-eMMC board

[oweals/u-boot.git] / arch / arm / dts / fsl-ls1046a.dtsi

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 359a9d13bf8e6397d462b84a40240204fbfb6271..f46707d320111bb95aa328993c37700bc797024f 100644 (file)
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -5,9 +5,7 @@
  *
  * Mingkai Hu <mingkai.hu@nxp.com>
  *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * SPDX-License-Identifier:    GPL-2.0+        X11
  */
 
 /include/ "skeleton64.dtsi"
@@ -216,5 +214,75 @@
                        big-endian;
                        status = "disabled";
                };
+
+               usb0: usb@2f00000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x2f00000 0x0 0x10000>;
+                       interrupts = <0 60 4>;
+                       dr_mode = "host";
+               };
+
+               usb1: usb@3000000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x3000000 0x0 0x10000>;
+                       interrupts = <0 61 4>;
+                       dr_mode = "host";
+               };
+
+               usb2: usb@3100000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x3100000 0x0 0x10000>;
+                       interrupts = <0 63 4>;
+                       dr_mode = "host";
+               };
+
+               pcie@3400000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03480000 0x0 0x40000   /* lut registers */
+                              0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
+                              0x40 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3500000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03580000 0x0 0x40000   /* lut registers */
+                              0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
+                              0x48 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       num-lanes = <2>;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3600000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03680000 0x0 0x40000   /* lut registers */
+                              0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
+                              0x50 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
        };
 };