arm: zynq: Remove ethernet alias for topic-miami

[oweals/u-boot.git] / arch / arm / dts / fsl-ls1046a.dtsi

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 87dd9976d154aa6fbad1a4a64f4374d131e55406..408e81e41570a35ccd30568ce75d9ceebd296bda 100644 (file)
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -151,6 +151,60 @@
                        clocks = <&clockgen 4 0>;
                };
 
+               lpuart0: serial@2950000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2950000 0x0 0x1000>;
+                       interrupts = <0 48 0x4>;
+                       clocks = <&clockgen 4 0>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart1: serial@2960000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2960000 0x0 0x1000>;
+                       interrupts = <0 49 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart2: serial@2970000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2970000 0x0 0x1000>;
+                       interrupts = <0 50 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart3: serial@2980000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2980000 0x0 0x1000>;
+                       interrupts = <0 51 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart4: serial@2990000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2990000 0x0 0x1000>;
+                       interrupts = <0 52 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart5: serial@29a0000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x29a0000 0x0 0x1000>;
+                       interrupts = <0 53 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
                qspi: quadspi@1550000 {
                        compatible = "fsl,vf610-qspi";
                        #address-cells = <1>;
@@ -162,5 +216,75 @@
                        big-endian;
                        status = "disabled";
                };
+
+               usb0: usb@2f00000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x2f00000 0x0 0x10000>;
+                       interrupts = <0 60 4>;
+                       dr_mode = "host";
+               };
+
+               usb1: usb@3000000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x3000000 0x0 0x10000>;
+                       interrupts = <0 61 4>;
+                       dr_mode = "host";
+               };
+
+               usb2: usb@3100000 {
+                       compatible = "fsl,layerscape-dwc3";
+                       reg = <0x0 0x3100000 0x0 0x10000>;
+                       interrupts = <0 63 4>;
+                       dr_mode = "host";
+               };
+
+               pcie@3400000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03480000 0x0 0x40000   /* lut registers */
+                              0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
+                              0x40 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3500000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03580000 0x0 0x40000   /* lut registers */
+                              0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
+                              0x48 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       num-lanes = <2>;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3600000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03680000 0x0 0x40000   /* lut registers */
+                              0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
+                              0x50 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
        };
 };