Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clk

[oweals/u-boot.git] / arch / arm / dts / fsl-ls1043a.dtsi

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 3cc20774c12a395ef5687cacd7c9fc6c511e4ffc..b159c3ca732e2dd2304d88f6a77cb8959f8da78f 100644 (file)
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright (C) 2014-2015, Freescale Semiconductor
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+        X11
  */
 
 /include/ "skeleton64.dtsi"
@@ -71,6 +70,14 @@
                        status = "disabled";
                };
 
+               esdhc: esdhc@1560000 {
+                       compatible = "fsl,esdhc";
+                       reg = <0x0 0x1560000 0x0 0x10000>;
+                       interrupts = <0 62 0x4>;
+                       big-endian;
+                       bus-width = <4>;
+               };
+
                ifc: ifc@1530000 {
                        compatible = "fsl,ifc", "simple-bus";
                        reg = <0x0 0x1530000 0x0 0x10000>;
@@ -280,5 +287,15 @@
                        ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
                                  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                };
+
+               sata: sata@3200000 {
+                       compatible = "fsl,ls1043a-ahci";
+                       reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+                              0x0 0x20140520 0x0 0x4>;  /* ecc sata addr*/
+                       reg-names = "sata-base", "ecc-addr";
+                       interrupts = <0 69 4>;
+                       clocks = <&clockgen 4 0>;
+                       status = "disabled";
+               };
        };
 };