Merge branch 'master' of git://git.denx.de/u-boot
[oweals/u-boot.git] / arch / arm / dts / bcm63158.dtsi
index 6a3fbc90939b22cdba221b1d601293fce511e453..7dd2858438491aa6c250c2610cfa2189dafca69f 100644 (file)
        #address-cells = <2>;
        #size-cells = <2>;
 
+       aliases {
+               spi0 = &hsspi;
+       };
+
        cpus {
                #address-cells = <2>;
                #size-cells = <0>;
                        clock-frequency = <0xbebc200>;
                        u-boot,dm-pre-reloc;
                };
+
+               hsspi_pll: hsspi-pll {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clocks = <&periph_osc>;
+                       clock-mult = <2>;
+                       clock-div = <1>;
+               };
+
+               refclk50mhz: refclk50mhz {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <50000000>;
+               };
        };
 
        ubus {
                        status = "disabled";
                };
 
+               leds: led-controller@ff800800 {
+                       compatible = "brcm,bcm6858-leds";
+                       reg = <0x0 0xff800800 0x0 0xe4>;
+
+                       status = "disabled";
+               };
+
                wdt1: watchdog@ff800480 {
                        compatible = "brcm,bcm6345-wdt";
                        reg = <0x0 0xff800480 0x0 0x14>;
-                       clocks = <&periph_osc>;
+                       clocks = <&refclk50mhz>;
                };
 
                wdt2: watchdog@ff8004c0 {
                        compatible = "brcm,bcm6345-wdt";
                        reg = <0x0 0xff8004c0 0x0 0x14>;
-                       clocks = <&periph_osc>;
+                       clocks = <&refclk50mhz>;
                };
 
                wdt-reboot {
                        compatible = "wdt-reboot";
                        wdt = <&wdt1>;
                };
+
+               gpio0: gpio-controller@0xff800500 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x0 0xff800500 0x0 0x4>,
+                             <0x0 0xff800520 0x0 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio1: gpio-controller@0xff800504 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x0 0xff800504 0x0 0x4>,
+                             <0x0 0xff800524 0x0 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio2: gpio-controller@0xff800508 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x0 0xff800508 0x0 0x4>,
+                             <0x0 0xff800528 0x0 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio3: gpio-controller@0xff80050c {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x0 0xff80050c 0x0 0x4>,
+                             <0x0 0xff80052c 0x0 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio4: gpio-controller@0xff800510 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x0 0xff800510 0x0 0x4>,
+                             <0x0 0xff800530 0x0 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio5: gpio-controller@0xff800514 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x0 0xff800514 0x0 0x4>,
+                             <0x0 0xff800534 0x0 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio6: gpio-controller@0xff800518 {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x0 0xff800518 0x0 0x4>,
+                             <0x0 0xff800538 0x0 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio7: gpio-controller@0xff80051c {
+                       compatible = "brcm,bcm6345-gpio";
+                       reg = <0x0 0xff80051c 0x0 0x4>,
+                             <0x0 0xff80053c 0x0 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       status = "disabled";
+               };
+
+               hsspi: spi-controller@ff801000 {
+                       compatible = "brcm,bcm6328-hsspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xff801000 0x0 0x600>;
+                       clocks = <&hsspi_pll>, <&hsspi_pll>;
+                       clock-names = "hsspi", "pll";
+                       spi-max-frequency = <100000000>;
+                       num-cs = <8>;
+
+                       status = "disabled";
+               };
+
+               nand: nand-controller@ff801800 {
+                       compatible = "brcm,nand-bcm63158",
+                                    "brcm,brcmnand-v5.0",
+                                    "brcm,brcmnand";
+                       reg-names = "nand", "nand-int-base", "nand-cache";
+                       reg = <0x0 0xff801800 0x0 0x180>,
+                             <0x0 0xff802000 0x0 0x10>,
+                             <0x0 0xff801c00 0x0 0x200>;
+                       parameter-page-big-endian = <0>;
+
+                       status = "disabled";
+               };
        };
 };