arm: dts: lx2160ardb: add DPMAC and PHY nodes

[oweals/u-boot.git] / arch / arm / dts / ast2500-u-boot.dtsi

diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index c95a7ba835a0bbb17ea53891c2d2d3a9cd67c07c..8ac42157455703b922eb467486ebacc9350c7555 100644 (file)
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,5 @@
 #include <dt-bindings/clock/ast2500-scu.h>
+#include <dt-bindings/reset/ast2500-reset.h>
 
 #include "ast2500.dtsi"
 
@@ -11,12 +12,21 @@
                #reset-cells = <1>;
        };
 
+       rst: reset-controller {
+               u-boot,dm-pre-reloc;
+               compatible = "aspeed,ast2500-reset";
+               aspeed,wdt = <&wdt1>;
+               #reset-cells = <1>;
+       };
+
        sdrammc: sdrammc@1e6e0000 {
                u-boot,dm-pre-reloc;
                compatible = "aspeed,ast2500-sdrammc";
                reg = <0x1e6e0000 0x174
                        0x1e6e0200 0x1d4 >;
+               #reset-cells = <1>;
                clocks = <&scu PLL_MPLL>;
+               resets = <&rst AST_RESET_SDRAM>;
        };
 
        ahb {
@@ -25,29 +35,54 @@
                apb {
                        u-boot,dm-pre-reloc;
 
-                       timer: timer@1e782000 {
-                               u-boot,dm-pre-reloc;
+                       sdhci0: sdhci@1e740100 {
+                               compatible = "aspeed,ast2500-sdhci";
+                               reg = <0x1e740100>;
+                               #reset-cells = <1>;
+                               clocks = <&scu BCLK_SDCLK>;
+                               resets = <&rst AST_RESET_SDIO>;
                        };
 
-                       uart1: serial@1e783000 {
-                               clocks = <&scu PCLK_UART1>;
+                       sdhci1: sdhci@1e740200 {
+                               compatible = "aspeed,ast2500-sdhci";
+                               reg = <0x1e740200>;
+                               #reset-cells = <1>;
+                               clocks = <&scu BCLK_SDCLK>;
+                               resets = <&rst AST_RESET_SDIO>;
                        };
+               };
 
-                       uart2: serial@1e78d000 {
-                               clocks = <&scu PCLK_UART2>;
-                       };
+       };
+};
 
-                       uart3: serial@1e78e000 {
-                               clocks = <&scu PCLK_UART3>;
-                       };
+&uart1 {
+       clocks = <&scu PCLK_UART1>;
+};
 
-                       uart4: serial@1e78f000 {
-                               clocks = <&scu PCLK_UART4>;
-                       };
+&uart2 {
+       clocks = <&scu PCLK_UART2>;
+};
 
-                       uart5: serial@1e784000 {
-                               clocks = <&scu PCLK_UART5>;
-                       };
-               };
-       };
+&uart3 {
+       clocks = <&scu PCLK_UART3>;
+};
+
+&uart4 {
+       clocks = <&scu PCLK_UART4>;
+};
+
+&uart5 {
+       clocks = <&scu PCLK_UART5>;
+};
+
+&timer {
+       u-boot,dm-pre-reloc;
+};
+
+&mac0 {
+       clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+};
+
+&mac1 {
+       clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
 };