stdout-path = "serial0:115200n8";
};
+ aliases {
+ i2c0 = &cpm_i2c0;
+ spi0 = &cps_spi1;
+ };
+
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
-&i2c0 {
+/* Accessible over the mini-USB CON9 connector on the main board */
+&uart0 {
status = "okay";
- clock-frequency = <100000>;
};
-&spi0 {
- status = "okay";
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-10]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 0 0 0 0 0 0 0 3 >;
+};
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
+&cpm_pinctl {
+ /* MPP Bus:
+ * [0-31] = 0xff: Keep default CP0_shared_pins
+ * [11] CLKOUT_MPP_11 (out)
+ * [23] LINK_RD_IN_CP2CP (in)
+ * [25] CLKOUT_MPP_25 (out)
+ * [29] AVS_FB_IN_CP2CP (in)
+ * [32,34] GE_MDIO/MDC
+ * [33] GPIO: GE_INT#/push button/Wake
+ * [35] MSS_GPIO[3]: MSS_PWDN
+ * [36] MSS_GPIO[5]: MSS_VTT_EN
+ * [37-38] I2C0
+ * [39] PTP_CLK
+ * [40-41] SATA[0/1]_PRESENT_ACTIVEn
+ * [42-43] XG_MDC/XG_MDIO (XSMI)
+ * [44-55] RGMII1
+ * [56-62] SD
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0x7 0x0 0x7 0xa 0xa 0x2 0x2 0x5
+ 0x9 0x9 0x8 0x8 0x1 0x1 0x1 0x1 0x1 0x1
+ 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
+ 0xe 0xe 0xe>;
+};
- partition@0 {
- label = "U-Boot";
- reg = <0 0x200000>;
- };
- partition@400000 {
- label = "Filesystem";
- reg = <0x200000 0xce0000>;
- };
- };
+&cpm_comphy {
+ /* Serdes Configuration:
+ * Lane 0: PCIe0 (x1)
+ * Lane 1: SATA0
+ * Lane 2: SFI (10G)
+ * Lane 3: SATA1
+ * Lane 4: USB3_HOST1
+ * Lane 5: PCIe2 (x1)
+ */
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+ phy1 {
+ phy-type = <PHY_TYPE_SATA0>;
+ };
+ phy2 {
+ phy-type = <PHY_TYPE_SFI>;
+ };
+ phy3 {
+ phy-type = <PHY_TYPE_SATA1>;
+ };
+ phy4 {
+ phy-type = <PHY_TYPE_USB3_HOST1>;
+ };
+ phy5 {
+ phy-type = <PHY_TYPE_PEX2>;
};
};
-/* Accessible over the mini-USB CON9 connector on the main board */
-&uart0 {
+/* CON6 on CP0 expansion */
+&cpm_pcie0 {
status = "okay";
};
+&cpm_pcie1 {
+ status = "disabled";
+};
/* CON5 on CP0 expansion */
&cpm_pcie2 {
};
&cpm_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
status = "okay";
};
-/* CON5 on CP1 expansion */
-&cps_pcie2 {
- status = "okay";
-};
-
-&cps_i2c0 {
+&cpm_utmi0 {
status = "okay";
- clock-frequency = <100000>;
};
-/* CON4 on CP1 expansion */
-&cps_sata0 {
+&cpm_utmi1 {
status = "okay";
};
-/* CON9 on CP1 expansion */
-&cps_usb3_0 {
+&cpm_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sdhci_pins>;
+ bus-width = <4>;
status = "okay";
};
-/* CON10 on CP1 expansion */
-&cps_usb3_1 {
- status = "okay";
+&cps_pinctl {
+ /* MPP Bus:
+ * [0-11] RGMII0
+ * [13-16] SPI1
+ * [27,31] GE_MDIO/MDC
+ * [28] SATA1_PRESENT_ACTIVEn
+ * [29-30] UART0
+ * [32-62] = 0xff: Keep default CP1_shared_pins
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
+ 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0x9 0xa
+ 0xA 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff>;
};
-&cpm_comphy {
- /*
- * Serdes Configuration:
- * Lane 0: SGMII2
- * Lane 1: USB3_HOST0
- * Lane 2: KR (10G)
- * Lane 3: SATA1
- * Lane 4: USB3_HOST1
- * Lane 5: PEX2x1
+&cps_comphy {
+ /* Serdes Configuration:
+ * Lane 0: PCIe0 (x1)
+ * Lane 1: SATA0
+ * Lane 2: SFI (10G)
+ * Lane 3: SATA1
+ * Lane 4: PCIe1 (x1)
+ * Lane 5: PCIe2 (x1)
*/
phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <PHY_TYPE_PEX0>;
};
-
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <PHY_TYPE_SATA0>;
};
-
phy2 {
- phy-type = <PHY_TYPE_KR>;
+ phy-type = <PHY_TYPE_SFI>;
};
-
phy3 {
phy-type = <PHY_TYPE_SATA1>;
};
-
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-type = <PHY_TYPE_PEX1>;
};
-
phy5 {
phy-type = <PHY_TYPE_PEX2>;
};
};
-&cps_comphy {
- /*
- * Serdes Configuration:
- * Lane 0: SGMII2
- * Lane 1: USB3_HOST0
- * Lane 2: KR (10G)
- * Lane 3: SATA1
- * Lane 4: Unconnected
- * Lane 5: PEX2x1
- */
- phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
- };
+/* CON6 on CP1 expansion */
+&cps_pcie0 {
+ status = "okay";
+};
- phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- };
+&cps_pcie1 {
+ status = "okay";
+};
- phy2 {
- phy-type = <PHY_TYPE_KR>;
- };
+/* CON5 on CP1 expansion */
+&cps_pcie2 {
+ status = "okay";
+};
- phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- };
+&cps_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cps_spi1_pins>;
+ status = "okay";
- phy4 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
- };
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
- phy5 {
- phy-type = <PHY_TYPE_PEX2>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xce0000>;
+ };
+ };
};
};
-&cpm_utmi0 {
+/* CON4 on CP1 expansion */
+&cps_sata0 {
status = "okay";
};
-&cpm_utmi1 {
+/* CON9 on CP1 expansion */
+&cps_usb3_0 {
+ status = "okay";
+};
+
+/* CON10 on CP1 expansion */
+&cps_usb3_1 {
status = "okay";
};
&cps_utmi0 {
status = "okay";
};
+
+&cpm_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&cpm_ethernet {
+ status = "okay";
+};
+
+&cpm_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
projects / oweals / u-boot.git / blobdiff