ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / dts / armada-7040-db.dts

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index b8fe5a9cb93dcf9e4e49505800f182d7fb8b58df..cfd2b4baf34d8b91cb4a9a74b1d676a5f4a85496 100644 (file)
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -42,6 +42,7 @@
 
 /*
  * Device Tree file for Marvell Armada 7040 Development board platform
+ * Boot device: SPI NOR, 0x32 (SW3)
  */
 
 #include "armada-7040.dtsi"
@@ -66,36 +67,14 @@
        };
 };
 
-&i2c0 {
-       status = "okay";
-       clock-frequency = <100000>;
-};
-
-&spi0 {
-       status = "okay";
-
-       spi-flash@0 {
-               #address-cells = <1>;
-               #size-cells = <1>;
-               compatible = "jedec,spi-nor";
-               reg = <0>;
-               spi-max-frequency = <10000000>;
-
-               partitions {
-                       compatible = "fixed-partitions";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-
-                       partition@0 {
-                               label = "U-Boot";
-                               reg = <0 0x200000>;
-                       };
-                       partition@400000 {
-                               label = "Filesystem";
-                               reg = <0x200000 0xce0000>;
-                       };
-               };
-       };
+&ap_pinctl {
+          /* MPP Bus:
+           * SDIO  [0-5]
+           * UART0 [11,19]
+           */
+                 /* 0 1 2 3 4 5 6 7 8 9 */
+       pin-func = < 1 1 1 1 1 1 0 0 0 0
+                    0 3 0 0 0 0 0 0 0 3 >;
 };
 
 &uart0 {
@@ -108,11 +87,37 @@
 };
 
 &cpm_i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cpm_i2c0_pins>;
        status = "okay";
        clock-frequency = <100000>;
 };
 
+&cpm_pinctl {
+               /* MPP Bus:
+                * TDM   [0-11]
+                * SPI   [13-16]
+                * SATA1 [28]
+                * UART0 [29-30]
+                * SMI   [32,34]
+                * XSMI  [35-36]
+                * I2C   [37-38]
+                * RGMII1[44-55]
+                * SD    [56-62]
+                */
+               /*   0   1   2   3   4   5   6   7   8   9 */
+       pin-func = < 4   4   4   4   4   4   4   4   4   4
+                    4   4   0   3   3   3   3   0   0   0
+                    0   0   0   0   0   0   0   0   9   0xA
+                    0xA 0   7   0   7   7   7   2   2   0
+                    0   0   0   0   1   1   1   1   1   1
+                    1   1   1   1   1   1   0xE 0xE 0xE 0xE
+                    0xE 0xE 0xE >;
+};
+
 &cpm_spi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cpm_spi0_pins>;
        status = "okay";
 
        spi-flash@0 {
@@ -154,8 +159,8 @@
 
 &cpm_comphy {
        phy0 {
-               phy-type = <PHY_TYPE_SGMII2>;
-               phy-speed = <PHY_SPEED_3_125G>;
+               phy-type = <PHY_TYPE_SGMII1>;
+               phy-speed = <PHY_SPEED_1_25G>;
        };
 
        phy1 {
@@ -164,8 +169,7 @@
        };
 
        phy2 {
-               phy-type = <PHY_TYPE_SGMII0>;
-               phy-speed = <PHY_SPEED_1_25G>;
+               phy-type = <PHY_TYPE_SFI>;
        };
 
        phy3 {
@@ -191,3 +195,47 @@
 &cpm_utmi1 {
        status = "okay";
 };
+
+&ap_sdhci0 {
+       status = "okay";
+       bus-width = <4>;
+       no-1-8-v;
+       non-removable;
+};
+
+&cpm_sdhci0 {
+       status = "okay";
+       bus-width = <4>;
+       no-1-8-v;
+       non-removable;
+};
+
+&cpm_mdio {
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+       };
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+};
+
+&cpm_ethernet {
+       status = "okay";
+};
+
+&cpm_eth0 {
+       status = "okay";
+       phy-mode = "sfi"; /* lane-2 */
+};
+
+&cpm_eth1 {
+       status = "okay";
+       phy = <&phy0>;
+       phy-mode = "sgmii";
+};
+
+&cpm_eth2 {
+       status = "okay";
+       phy = <&phy1>;
+       phy-mode = "rgmii-id";
+};