Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clk
[oweals/u-boot.git] / arch / arm / dts / armada-38x-controlcenterdc.dts
index d183fd75024dec674fbcb05f12416e3c7ca79b15..5063a798df76b39bedbad380915befcbe254690c 100644 (file)
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Device Tree file for the Guntermann & Drunck ControlCenter-Compact board
  *
@@ -9,8 +10,6 @@
  * Copyright (C) 2014 Marvell
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 /dts-v1/;
                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
 
                internal-regs {
-                       spi0: spi@10600 {
-                               status = "okay";
-                               sc16is741: sc16is741@0 {
-                                       compatible = "nxp,sc16is741";
-                                       reg = <0>;
-                                       clocks = <&sc16isclk>;
-                                       spi-max-frequency = <4000000>;
-                                       interrupt-parent = <&gpio0>;
-                                       interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-                                       gpio-controller;
-                                       #gpio-cells = <2>;
-                               };
-                       };
-
-                       spi1: spi@10680 {
-                               status = "okay";
-                               u-boot,dm-pre-reloc;
-                               spi-flash@0 {
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
-                                       compatible = "n25q016a";
-                                       reg = <0>; /* Chip select 0 */
-                                       spi-max-frequency = <108000000>;
-                               };
-                               spi-flash@1 {
-                                       #address-cells = <1>;
-                                       #size-cells = <1>;
-                                       compatible = "n25q128a11";
-                                       reg = <1>; /* Chip select 1 */
-                                       spi-max-frequency = <108000000>;
-                                       u-boot,dm-pre-reloc;
-                               };
-                       };
-
                        I2C0: i2c@11000 {
                                status = "okay";
                                clock-frequency = <1000000>;
                        };
                };
 
-               pcie-controller {
+               pcie {
                        status = "okay";
                        /*
                         * The two PCIe units are accessible through
                };
        };
 };
+
+&spi0 {
+       status = "okay";
+       sc16is741: sc16is741@0 {
+               compatible = "nxp,sc16is741";
+               reg = <0>;
+               clocks = <&sc16isclk>;
+               spi-max-frequency = <4000000>;
+               interrupt-parent = <&gpio0>;
+               interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+};
+
+&spi1 {
+       status = "okay";
+       u-boot,dm-pre-reloc;
+       spi-flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "n25q016a", "jedec,spi-nor";
+               reg = <0>; /* Chip select 0 */
+               spi-max-frequency = <108000000>;
+       };
+       spi-flash@1 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "n25q128a11", "jedec,spi-nor";
+               reg = <1>; /* Chip select 1 */
+               spi-max-frequency = <108000000>;
+               u-boot,dm-pre-reloc;
+       };
+};