tegra20: add clock_set_pllout function
[oweals/u-boot.git] / arch / arm / cpu / tegra20-common / warmboot_avp.c
index 80a5a15decf6e0082d1fa109cbae006ba94b4008..bc46606892520cc5d7234aa8fb846b15eee3f1cd 100644 (file)
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/flow.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/warmboot.h>
 #include "warmboot_avp.h"
 
 #define DEBUG_RESET_CORESIGHT
@@ -58,7 +58,7 @@ void wb_start(void)
                                        /* no input, no clobber list */
        );
 
-       if (reg != AP20_WB_RUN_ADDRESS)
+       if (reg != NV_WB_RUN_ADDRESS)
                goto do_reset;
 
        /* Are we running with AVP? */
@@ -214,7 +214,7 @@ void wb_start(void)
 
        reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
              PLLM_OUT1_RATIO_VAL_8;
-       writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out);
+       writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
 
        reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
              SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |