Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[oweals/u-boot.git] / arch / arm / cpu / armv8 / zynqmp / cpu.c

diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 6fae03c1af5c2208e590fcf2cf8e3f32d96b52e1..b0f12955a1ffac03ec37f3ccf87ac52d687fee51 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/armv8/mmu.h>
 #include <asm/io.h>
 
 #define ZYNQ_SILICON_VER_MASK  0xF000
@@ -15,14 +16,91 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct mm_region zynqmp_mem_map[] = {
+       {
+               .virt = 0x0UL,
+               .phys = 0x0UL,
+               .size = 0x80000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0x80000000UL,
+               .phys = 0x80000000UL,
+               .size = 0x70000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0xf8000000UL,
+               .phys = 0xf8000000UL,
+               .size = 0x07e00000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0xffe00000UL,
+               .phys = 0xffe00000UL,
+               .size = 0x00200000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0x400000000UL,
+               .phys = 0x400000000UL,
+               .size = 0x200000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0x600000000UL,
+               .phys = 0x600000000UL,
+               .size = 0x800000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0xe00000000UL,
+               .phys = 0xe00000000UL,
+               .size = 0xf200000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+struct mm_region *mem_map = zynqmp_mem_map;
+
+u64 get_page_table_size(void)
+{
+       return 0x14000;
+}
+
+static unsigned int zynqmp_get_silicon_version_secure(void)
+{
+       u32 ver;
+
+       ver = readl(&csu_base->version);
+       ver &= ZYNQMP_SILICON_VER_MASK;
+       ver >>= ZYNQMP_SILICON_VER_SHIFT;
+
+       return ver;
+}
+
 unsigned int zynqmp_get_silicon_version(void)
 {
+       if (current_el() == 3)
+               return zynqmp_get_silicon_version_secure();
+
        gd->cpu_clk = get_tbclk();
 
        switch (gd->cpu_clk) {
+       case 0 ... 1000000:
+               return ZYNQMP_CSU_VERSION_VELOCE;
        case 50000000:
                return ZYNQMP_CSU_VERSION_QEMU;
+       case 4000000:
+               return ZYNQMP_CSU_VERSION_EP108;
        }
 
-       return ZYNQMP_CSU_VERSION_EP108;
+       return ZYNQMP_CSU_VERSION_SILICON;
 }