Merge git://git.denx.de/u-boot-sunxi

[oweals/u-boot.git] / arch / arm / cpu / armv8 / start.S

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index deb44a895fdab9aeaabfccfa9f9be7f6a57f0549..7a98a1c95d24af2caddfba824182e30268ceb562 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -19,7 +19,18 @@
 
 .globl _start
 _start:
+#if defined(LINUX_KERNEL_IMAGE_HEADER)
+#include <asm/boot0-linux-kernel-header.h>
+#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include <asm/arch/boot0.h>
+#else
        b       reset
+#endif
 
        .align 3
 
@@ -43,6 +54,37 @@ _bss_end_ofs:
        .quad   __bss_end - _start
 
 reset:
+       /* Allow the board to save important registers */
+       b       save_boot_params
+.globl save_boot_params_ret
+save_boot_params_ret:
+
+#if CONFIG_POSITION_INDEPENDENT
+       /*
+        * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
+        * executed at a different address than it was linked at.
+        */
+pie_fixup:
+       adr     x0, _start              /* x0 <- Runtime value of _start */
+       ldr     x1, _TEXT_BASE          /* x1 <- Linked value of _start */
+       sub     x9, x0, x1              /* x9 <- Run-vs-link offset */
+       adr     x2, __rel_dyn_start     /* x2 <- Runtime &__rel_dyn_start */
+       adr     x3, __rel_dyn_end       /* x3 <- Runtime &__rel_dyn_end */
+pie_fix_loop:
+       ldp     x0, x1, [x2], #16       /* (x0, x1) <- (Link location, fixup) */
+       ldr     x4, [x2], #8            /* x4 <- addend */
+       cmp     w1, #1027               /* relative fixup? */
+       bne     pie_skip_reloc
+       /* relative fix: store addend plus offset at dest location */
+       add     x0, x0, x9
+       add     x4, x4, x9
+       str     x4, [x0]
+pie_skip_reloc:
+       cmp     x2, x3
+       b.lo    pie_fix_loop
+pie_fixup_done:
+#endif
+
 #ifdef CONFIG_SYS_RESET_SCTRL
        bl reset_sctrl
 #endif
@@ -71,6 +113,20 @@ reset:
        msr     cpacr_el1, x0                   /* Enable FP/SIMD */
 0:
 
+       /*
+        * Enable SMPEN bit for coherency.
+        * This register is not architectural but at the moment
+        * this bit should be set for A53/A57/A72.
+        */
+#ifdef CONFIG_ARMV8_SET_SMPEN
+       switch_el x1, 3f, 1f, 1f
+3:
+       mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
+       orr     x0, x0, #0x40
+       msr     S3_1_c15_c2_1, x0
+1:
+#endif
+
        /* Apply ARM core specific erratas */
        bl      apply_core_errata
 
@@ -84,7 +140,11 @@ reset:
        /* Processor specific initialization */
        bl      lowlevel_init
 
-#ifdef CONFIG_ARMV8_MULTIENTRY
+#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
+       branch_if_master x0, x1, master_cpu
+       b       spin_table_secondary_jump
+       /* never return */
+#elif defined(CONFIG_ARMV8_MULTIENTRY)
        branch_if_master x0, x1, master_cpu
 
        /*
@@ -96,10 +156,8 @@ slave_cpu:
        ldr     x0, [x1]
        cbz     x0, slave_cpu
        br      x0                      /* branch to the given address */
-master_cpu:
-       /* On the master CPU */
 #endif /* CONFIG_ARMV8_MULTIENTRY */
-
+master_cpu:
        bl      _main
 
 #ifdef CONFIG_SYS_RESET_SCTRL
@@ -140,7 +198,10 @@ reset_sctrl:
 WEAK(apply_core_errata)
 
        mov     x29, lr                 /* Save LR */
-       /* For now, we support Cortex-A57 specific errata only */
+       /* For now, we support Cortex-A53, Cortex-A57 specific errata */
+
+       /* Check if we are running on a Cortex-A53 core */
+       branch_if_a53_core x0, apply_a53_core_errata
 
        /* Check if we are running on a Cortex-A57 core */
        branch_if_a57_core x0, apply_a57_core_errata
@@ -148,6 +209,25 @@ WEAK(apply_core_errata)
        mov     lr, x29                 /* Restore LR */
        ret
 
+apply_a53_core_errata:
+
+#ifdef CONFIG_ARM_ERRATA_855873
+       mrs     x0, midr_el1
+       tst     x0, #(0xf << 20)
+       b.ne    0b
+
+       mrs     x0, midr_el1
+       and     x0, x0, #0xf
+       cmp     x0, #3
+       b.lt    0b
+
+       mrs     x0, S3_1_c15_c2_0       /* cpuactlr_el1 */
+       /* Enable data cache clean as data cache clean/invalidate */
+       orr     x0, x0, #1 << 44
+       msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+#endif
+       b 0b
+
 apply_a57_core_errata:
 
 #ifdef CONFIG_ARM_ERRATA_828024
@@ -214,7 +294,9 @@ WEAK(lowlevel_init)
        ldr     x1, =GICC_BASE
        bl      gic_init_secure_percpu
 #endif
+#endif
 
+#ifdef CONFIG_ARMV8_MULTIENTRY
        branch_if_master x0, x1, 2f
 
        /*
@@ -232,9 +314,17 @@ WEAK(lowlevel_init)
        /*
         * All slaves will enter EL2 and optionally EL1.
         */
+       adr     x4, lowlevel_in_el2
+       ldr     x5, =ES_TO_AARCH64
        bl      armv8_switch_to_el2
+
+lowlevel_in_el2:
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+       adr     x4, lowlevel_in_el1
+       ldr     x5, =ES_TO_AARCH64
        bl      armv8_switch_to_el1
+
+lowlevel_in_el1:
 #endif
 
 #endif /* CONFIG_ARMV8_MULTIENTRY */
@@ -246,12 +336,10 @@ ENDPROC(lowlevel_init)
 
 WEAK(smp_kick_all_cpus)
        /* Kick secondary cpus up by SGI 0 interrupt */
-       mov     x29, lr                 /* Save LR */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
        ldr     x0, =GICD_BASE
-       bl      gic_kick_secondary_cpus
+       b       gic_kick_secondary_cpus
 #endif
-       mov     lr, x29                 /* Restore LR */
        ret
 ENDPROC(smp_kick_all_cpus)
 
@@ -270,3 +358,7 @@ ENTRY(c_runtime_cpu_setup)
 
        ret
 ENDPROC(c_runtime_cpu_setup)
+
+WEAK(save_boot_params)
+       b       save_boot_params_ret    /* back to my caller */
+ENDPROC(save_boot_params)