+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014-2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright 2019 NXP
*
* Extracted from armv8/start.S
*/
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
- mov w3, w2
- ands w3, w3, #SVR_WO_E << 8
- mov w4, #SVR_LS1043A << 8
+ lsr w3, w2, #16
+ ldr w4, =SVR_DEV(SVR_LS1043A)
cmp w3, w4
b.ne 1f
ands w2, w2, #0xff
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
-#ifdef CONFIG_FSL_LSCH3
+ /* unmask SError and abort */
+ msr daifclr, #4
+
+ /* Set HCR_EL2[AMO] so SError @EL2 is taken */
+ mrs x0, hcr_el2
+ orr x0, x0, #0x20 /* AMO */
+ msr hcr_el2, x0
+ isb
+
+ switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
+1:
+
+#if defined (CONFIG_SYS_FSL_HAS_CCN504)
/* Set Wuo bit for RN-I 20 */
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_ARCH_LS2080A
ldr x0, =CCI_AUX_CONTROL_BASE(20)
ldr x1, =0x00000010
bl ccn504_set_aux
*/
bl get_svr
lsr w0, w0, #16
- ldr w1, =SVR_DEV_LS2080A
+ ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */
#endif
#endif
+100:
branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
#endif
2:
+ switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
+1:
#ifdef CONFIG_FSL_TZPC_BP147
/* Set Non Secure access for all devices protected via TZPC */
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
*/
bl get_svr
lsr w0, w0, #16
- ldr w1, =SVR_DEV_LS2080A
+ ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
* placeholders.
*/
- ldr x1, =TZASC_GATE_KEEPER(0)
- ldr w0, [x1] /* Filter 0 Gate Keeper Register */
- orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
- str w0, [x1]
- ldr x1, =TZASC_GATE_KEEPER(1)
- ldr w0, [x1] /* Filter 0 Gate Keeper Register */
- orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
- str w0, [x1]
+.macro tzasc_prog, xreg
- ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
- ldr w0, [x1] /* Region-0 Attributes Register */
- orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
- orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
- str w0, [x1]
+ mov x12, TZASC1_BASE
+ mov x16, #0x10000
+ mul x14, \xreg, x16
+ add x14, x14,x12
+ mov x1, #0x8
+ add x1, x1, x14
- ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
- ldr w0, [x1] /* Region-1 Attributes Register */
- orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
- orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
- str w0, [x1]
+ ldr w0, [x1] /* Filter 0 Gate Keeper Register */
+ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
+ str w0, [x1]
- ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
- ldr w0, [x1] /* Region-0 Access Register */
- mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
- str w0, [x1]
+ mov x1, #0x110
+ add x1, x1, x14
- ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
- ldr w0, [x1] /* Region-1 Attributes Register */
- mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
- str w0, [x1]
+ ldr w0, [x1] /* Region-0 Attributes Register */
+ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str w0, [x1]
+
+ mov x1, #0x114
+ add x1, x1, x14
+
+ ldr w0, [x1] /* Region-0 Access Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+.endm
+#ifdef CONFIG_FSL_TZASC_1
+ mov x13, #0
+ tzasc_prog x13
+
+#endif
+#ifdef CONFIG_FSL_TZASC_2
+ mov x13, #1
+ tzasc_prog x13
+
+#endif
isb
dsb sy
#endif
+100:
1:
#ifdef CONFIG_ARCH_LS1046A
+ switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
+1:
/* Initialize the L2 RAM latency */
mrs x1, S3_1_c11_c0_2
mov x0, #0x1C7
orr x1, x1, #0x80
msr S3_1_c11_c0_2, x1
isb
+100:
#endif
-#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_TFABOOT) && \
+ (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
bl fsl_ocram_init
#endif
ldr x1, =FSL_LSCH3_SVR
ldr w0, [x1]
ret
+#endif
+#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508)
hnf_pstate_poll:
- /* x0 has the desired status, return 0 for success, 1 for timeout
- * clobber x1, x2, x3, x4, x6, x7
+ /* x0 has the desired status, return only if operation succeed
+ * clobber x1, x2, x6
*/
mov x1, x0
- mov x7, #0 /* flag for timeout */
- mrs x3, cntpct_el0 /* read timer */
- add x3, x3, #1200 /* timeout after 100 microseconds */
+ mov w6, #8 /* HN-F node count */
mov x0, #0x18
movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
- mov w6, #8 /* HN-F node count */
1:
ldr x2, [x0]
cmp x2, x1 /* check status */
b.eq 2f
- mrs x4, cntpct_el0
- cmp x4, x3
- b.ls 1b
- mov x7, #1 /* timeout */
- b 3f
+ b 1b
2:
add x0, x0, #0x10000 /* move to next node */
subs w6, w6, #1
cbnz w6, 1b
-3:
- mov x0, x7
ret
hnf_set_pstate:
/*
* Return status in x0
* success 0
- * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
*/
mov x29, lr
- mov x8, #0
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
mov x0, #0x4 /* SFONLY status */
bl hnf_pstate_poll
- cbz x0, 1f
- mov x8, #1 /* timeout */
-1:
+
dsb sy
mov x0, #0x3 /* HNFPSTAT_FAM */
bl hnf_set_pstate
mov x0, #0xc /* FAM status */
bl hnf_pstate_poll
- cbz x0, 1f
- add x8, x8, #0x2
-1:
- mov x0, x8
+
+ mov x0, #0
mov lr, x29
ret
ENDPROC(__asm_flush_l3_dcache)
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
rev x0, x0 /* BE to LE conversion */
cpu_is_le:
ldr x5, [x11, #24]
- ldr x6, =IH_ARCH_DEFAULT
- cmp x6, x5
- b.eq 1f
+ cbz x5, 1f
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- adr x3, secondary_switch_to_el1
- ldr x4, =ES_TO_AARCH64
+ adr x4, secondary_switch_to_el1
+ ldr x5, =ES_TO_AARCH64
#else
- ldr x3, [x11]
- ldr x4, =ES_TO_AARCH32
+ ldr x4, [x11]
+ ldr x5, =ES_TO_AARCH32
#endif
bl secondary_switch_to_el2
1:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- adr x3, secondary_switch_to_el1
+ adr x4, secondary_switch_to_el1
#else
- ldr x3, [x11]
+ ldr x4, [x11]
#endif
- ldr x4, =ES_TO_AARCH64
+ ldr x5, =ES_TO_AARCH64
bl secondary_switch_to_el2
ENDPROC(secondary_boot_func)
ENTRY(secondary_switch_to_el2)
- switch_el x5, 1f, 0f, 0f
+ switch_el x6, 1f, 0f, 0f
0: ret
-1: armv8_switch_to_el2_m x3, x4, x5
+1: armv8_switch_to_el2_m x4, x5, x6
ENDPROC(secondary_switch_to_el2)
ENTRY(secondary_switch_to_el1)
/* physical address of this cpus spin table element */
add x11, x1, x0
- ldr x3, [x11]
+ ldr x4, [x11]
ldr x5, [x11, #24]
- ldr x6, =IH_ARCH_DEFAULT
- cmp x6, x5
- b.eq 2f
+ cbz x5, 2f
- ldr x4, =ES_TO_AARCH32
+ ldr x5, =ES_TO_AARCH32
bl switch_to_el1
-2: ldr x4, =ES_TO_AARCH64
+2: ldr x5, =ES_TO_AARCH64
switch_to_el1:
- switch_el x5, 0f, 1f, 0f
+ switch_el x6, 0f, 1f, 0f
0: ret
-1: armv8_switch_to_el1_m x3, x4, x5
+1: armv8_switch_to_el1_m x4, x5, x6
ENDPROC(secondary_switch_to_el1)
/* Ensure that the literals used by the secondary boot code are
projects / oweals / u-boot.git / blobdiff